Performance of interface engineeredSiNx/ICL/InP/In0.53Ga0.47As/InP dopedchannel HIGFET's

SiN_x/InP/InGaAs doped channel passivated heterojunction insulated gate field effect transistors (HIGFETs) have been fabricated for the first time using an improved In-S interface control layer (ICL). The insulated gate HIGFETs exhibit very low gate leakage (10 nA@V_GS =±5 V) and I_DS (sat) of 250 mA/mm. The doped channel improves the DC characteristics and the HIGFETs show transconductance of 140-150 mS/mm (L_g=2 μm), f_t of 5-6 GHz (L_g=3 μm), and power gain of 14.2 dB at 3 GHz. The ICL HIGFET technology is promising for high frequency applications     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Analysis and design-optimization of LCC resonant inverter forhigh-frequency AC distributed power system

The analysis and design of an LCC resonant inverter for a 20 kHz AC distributed power system are presented. Several resonant converter topologies are assessed to determine their suitability for high efficiency power conversion, under resistive and reactive loads. Two LCC-resonant inverter designs were implemented. One with all switches operating with zero voltage switching (ZVS), and another with two switches operating with ZVS and two switches with zero current switching (ZCS). The experimental results are presented along with a performance comparison of the two versions     

Optoelectronic integrated systems based on free-space interconnectswith an arbitrary degree of space variance

It is appealing to contemplate how VLSI or wafer-scale integrated systems incorporating free-space optical interconnection might outperform purely electrically interconnected systems. This paper first provides a uniform treatment of a general class of optical interconnects based on a Fourier-plane imaging system with an array of sources in the object plane and an array of receptors in the image plane. Sources correspond to data outputs of processing “cells,” and receptors to their data inputs. A general abstract optical imaging model, capable of representing a large class of real systems, is analyzed to yield constructive upper bounds on system volume that are comparable to those arising from “3-D VLSI” computational models. These bounds, coupled with technologically derived constraints, form the heart of a design methodology for optoelectronic systems that uses electronic and optical elements each to their greatest advantage, and exploits the available spatial volume and power in the most efficient way. Many of these concepts are embodied in a demonstration project that seeks to implement a bit-serial, multiprocessing system with a radix-2 butterfly topology, and incorporates various new technology developments     

A high-current and high-temperature 6H-SiC thyristor

A 6H-SiC thyristor has been fabricated and characterized. A forward breakover voltage close to 100 V and a pulse switched current density of 5200 A/cm² have been demonstrated. The thyristor is shown to operate under pulse gate triggering for turn-on and turn-off, with a rise time of 43 ns and a fall time of less than 100 ns. The forward breakover voltage is found to decrease by only 4% when the operating temperature is increased from room temperature to 300°C. It is found that anode ohmic contact resistance dominates the device forward drop at high current densities     

Pulsed-current duty cycle dependence of electromigration-inducedstress generation in aluminum conductors

The effect of duty cycle of pulsed dc currents on the critical length-current density product, (jl_c), was measured using the Blech-Kinsbron edge-displacement technique [Thin Solid Films 25, 327 (1975)]. Unencapsulated Al edge-displacement segments mere stressed at various duty cycles and the critical lengths, the so-called “Blech lengths”, were measured. It was found that jl_c increased with decreasing duty cycle. We measured a factor of 2.6 increase in jl_c for the 25% duty cycle as compared to dc. This duty cycle dependence of Blech length implies that electromigration resistance for an integrated circuit would be increased for small duty cycle operation by increasing the fraction of interconnects which are sub-Blech-length and are not susceptible to EM damage     

Labelling 2-D geometric primitives using probabilistic relaxation:reducing the computational requirements

In previous work, an algorithm for matching geometric features was developed. Although the method worked well, it was demanding in computational resources when applied to large problems. The authors now present methods for reducing the computational requirements, without significantly affecting the reliability of the algorithm     

Temperature and modulation characteristics of resonant-cavitylight-emitting diodes

Resonant-cavity light-emitting diodes (RCLED) are novel, high-efficiency light-emitting diodes which employ optical microcavities. These diodes have higher intensities and higher spectral purity as compared to conventional LEDs. Analytical formulas are derived for the enhancement of the spontaneous emission along the optical axis of the cavity. The design rules for high-efficiency operation of RCLEDs are established. The temperature dependence of the emission intensity is analyzed in the range 20-80° and it is described by an exponential dependence with a characteristic temperature of 112 K. The modulation characteristics of RCLEDs exhibit 3 dB frequencies of 580 MHz. Eye diagrams at transmission rates of 622 Mb/s are wide open indicating the suitability of RCLEDs for high-speed data transmission