深亚微米集成电路的快速时域仿真技术

随着深亚微米集成电路技术的发展，集成电路的规模越来越大，工作频率越来越高，并正朝着系统集成的方向发展，因而在模拟速度，模拟精度和可模拟的电路规模等各个方面对电路仿真技术提出了新的要求。近年来，各种新的电路仿真方法和仿真系统用相继脱颖百出，并将取代那些传统的，已经无法适应深亚微米技术发展的电路仿真器。     

高峰值功率重频脉冲固体激光器

综述了高峰值功率重频脉冲固体激光器的发展现状，对其中的Ｑ开关、腔倒空、锁模等窄脉冲技术和放大技术进行了分析，展示了高峰值功率重频脉冲固体激光器的发展前景。     

激光微焊接质量的模糊识别技术研究

讨论了激光微焊点焊接质量的模糊识别的概念，数学模型及其应用方法，并介绍了系统的硬件组成。     

非接触式半导体少子寿命测试方法——微波反射法

介绍了一种非接触式用于测量少子寿命的微波反射法，并与通常的光电导衰退法进行了比较。     

T_C≥400°C高温PTC陶瓷的研制

利用国产原料，采用传统的陶瓷材料制备工艺，研制了居里温度ＴＣ≥４００°Ｃ的高温ＰＴＣ陶瓷，制成了居里温度ＴＣ＝４１２°Ｃ，电阻Ｒ≤１０３Ω，ｌｇ（Ｒｍａｘ／Ｒｍｉｎ）＝４的高性能ＰＴＣ热敏陶瓷材料     

Dynamic oxide voltage relaxation spectroscopy

A new method for trap characterization of oxidized silicon is described. The Dynamic Oxide Voltage Relaxation Spectroscopy (DOVRS) is an improved version of the formerly proposed Oxide Voltage Relaxation Spectroscopy (OVRS) technique which applies a periodic long duration constant current for tunneling injection. It has been demonstrated that the new technique can be used not only to separate and identify the oxide trap from interface trap, but also to separate and determine the centroid from the oxide trap density generated in the MOS system by the tunneling current stress. In the pulse constant current mode, the OVRS measurement can be completed instead of using the double current-voltage technique. Thus the new method results in more accurate and quicker measurements of the oxide trap centroid. Analytical expressions for computing the paramaters of the interface and oxide traps are derived. The effect of the channel carrier mobility on the spectroscopy is also considered. Two types of oxide and two types of interface traps were observed at a pulse constant Fowler-Nordheim current stress by the new method of DOVRS     

最大度为6的极大外平面图的完备色数

证明了最大度为６的极大外平面图的完备色数为７。     

Transient hot-electron effect and its impact on circuit reliability

Transient hot-electron effect and its impact on circuit reliability are investigated. The rate of device decay is monitored as a function of the gate pulse transient period. Simulation results reveal that excess charges during a fast turn off time may cause an increase in the maximum substrate current. This, along with our experimental data, identifies that transient excess carrier may cause the enhancement of device degradation under certain stress conditions. The enhancement factor of the degradation is a function of the gate pulse transient time. Correlation between the analysis based upon AC/DC measurement and calculations based upon transient simulation are shown in the paper. Better agreement with experimental data is obtained by using the transient analysis and on chip test/stress structures. The correlation between AC and DC stress data is also shown based on the impact ionization model. A hot-electron design guideline is proposed based on the circuit reliability analysis. This guideline can help improve the circuit reliability without adversely effecting the circuit performance.     

Robustly good trellis codes

The relationship between the distance properties of trellis codes and the computational effort and error performance of sequential decoding is studied and optimum distance profile (ODP) and optimum free distance (OFD) trellis codes are constructed for 8-PSK and 16 QAM modulation. A comparison of the performance of both the ODP and the OFD trellis codes reveals that neither class of codes results in the best trade-off between error performance and computational effort when sequential decoding is used. A new algorithm is then proposed to construct robustly good trellis codes for use with sequential decoding. New trellis codes with asymptotic coding gains up to 6.66 dB are obtained using this algorithm, and the new codes achieve nearly the same free distances as the OFD codes and nearly the same distance profiles as the ODP codes     

Low-voltage BiCMOS dynamic minimum circuit using a parallelcomparison algorithm for fuzzy controllers

The authors present a low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for VLSI implementation of fuzzy controllers. Using low-voltage BiCMOS dynamic circuits and a parallel comparison algorithm, a four-4-bit-input minimum circuit designed, based on a 1μm BiCMOS technology, shows a 9.5ns comparison time, which is a ×2.5 improvement in speed as compared to that based on CMOS technology