New efficient designs for XOR and XNOR functions on the transistorlevel

Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of transistors. The other one improves the performance of the prior method but two more transistors are utilized. Both of them have been fully simulated by HSPICE on a SUN SPARC 2 workstation     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states     

Two-dimensional simulation of silicon avalanche cathodes

The characteristics of silicon avalanche cathode as a novel electron emitting device with ultra-shallow p-n junctions have been studied using the two-dimensional device simulator PISCES-IIB. The steady-state simulation indicates that the nonplanar surface topology resulting from fabrication process causes current crowding near the edge of the emitting area where the surface step exists. Current crowding degrades the emission uniformity and also reduces the emission current under increased reverse bias. The nonplanar surface structure also causes punchthrough in the epitaxial layer as the reverse bias on the cathode increases. As a result, the percentage of the cathode current contributing to emission decreases, reducing the emission efficiency consequently. The simulation shows that the portion of the cathode current that flows through the emitting area drops to as much as 30% at cathode bias higher than 12 V, compared to the same current just after breakdown. This also affects the rate of increase in the total emission current which is the product of the emission efficiency and the overall cathode current     

Damage and strain in pseudomorphic vs relaxed GexSi1−x layers on Si(100) generated by Si ion irradiation

We compare both the strain and damage that 100 keV Si irradiation at room temperature introduces in pseudomorphic and relaxed Ge_xSi_1−x films grown on Si(100) substrates. The ion range is such that the Si/Ge_xSi_1−x interface is not significantly damaged. The amount of damage produced in pseudomorphic and relaxed Ge_xSi_1−x layers of similar x for irradiation doses up to 2.5 × 10¹⁴ Si/cm² is the same, which proves that a pre-existing uniform strain does not noticeably affect the irradiation-induced damage. However, the irradiation-induced strain does depend on the pre-existing strain of the samples. Possible interpretations are discussed. On leave from Inst. voor Kern en Stralingsfysika, Catholic University of Leuven, Belgium.     

Dependence of critical current density on microstructure and processing of high-Tc superconductors

Microstructural origins for reduced weak-link behavior in high-J_c melt-processed YBCO, spray pyrolyzed thick films of Tl-1223, metallic precursor Y-124 polycrystalline powder-in-tube (PIT) wires and PIT Bi-2212/2223 are discussed. Since the materials studied are the highest J_c, polycrystalline, high-T_c superconductors fabricated worldwide, the results provide important guidelines for further improvements in superconducting properties, thereby enabling practical applications of these materials. It is found that strongly linked current flow within domains of melt-processed 123 occurs effectively through a single crystal path. In c-axis oriented, polycrystalline Tl-1223 thick films, local in-plane texture has been found to play a crucial role in the reduced weak-link behavior. Formation of “colonies” of grains with a common c-axis and modest in-plane misorientation was observed. Furthermore, a colony boundary in general has a varying misorientation along the boundary. Large regions comprised primarily of low angle boundaries were observed. Percolative transport through a network of such small angle boundaries appears to provide the nonweak-linked current path. Although powder-in-tube BSCCO 2212 and 2223 also appear to have a “colony” microstructure, there are some important differences. Colonies in BSCCO consist of stacks of grains with similar c-axis orientation in contrast to colonies in Tl-1223 films where few grains are stacked on top of one another. Furthermore, most grains within a colony in BSCCO have the same lateral dimensions as that of the colony, resulting largely largely in “twist” boundaries. Further microstructural characterization of high-J_c PIT 2212 and 2223 is currently underway. In the case of Y-124 wires, weak macroscopic in-plane texture is found. Additional measurements are underway to determine if a sharper, local in-plane texture also exists. It is found that in three of the four types of superconductors studied, reduced weak-link behavior can be ascribed to some degree of biaxial alignment between grains, either on a “local” or a “global” scale.     

N个振荡器相互注入锁定同步振荡系统

本文对Ｎ个振荡器相互注入锁定同步振荡系统提出了一种通用的分析方法。建立了该系统的完整非线性等效模型，导出了系统的状态方程。对于各种不同电路形式的振荡系统，只要将具体的电路参数代入，就可计算其输出功率，功率合成效率及工作频率等参数，从而使这类系统的计算机辅助分析和设计成为可能。     

毫米波谐波振荡器的Volterra级数分析法

本文基于Ｖｏｌｔｅｒｒａ级数法和非线性转移函数理论，提出了一种分析毫米波谐波振荡器的新方法，给出了描述其非线性特性的决定方程，通过求解一组非线性代数方程，便可计算出谐波振荡器的振荡频率和幅度。文中给出了具体分析实例，并与谐波平衡法等进行了比较，结果表明：这种方法具有理论严密、准确性高、适用范围广等特点，特别是利用一次决定方程的结果作为其它非线性数值分析方法的初始估值，则可大大地节约计算时间，并容易     

Error monitoring issues for common channel signaling

Motivated by field data which showed a large number of link changeovers and incidences of link oscillations between in-service and out-of-service states in common channel signalling (CCS) networks, a number of analyses of the link error monitoring procedures in the SS7 protocol were performed by the authors. This paper summarizes the results obtained thus far and include the following: (a) results of an exact analysis of the performance of the error monitoring procedures under both random and bursty errors; (b) a demonstration that there exists a range of error rates within which the error monitoring procedures of SS7 may induce frequent changeovers and changebacks; (c) an analysis of the performance of the SS7 level-2 transmission protocol to determine the tolerable error rates within which the delay requirements can be met; (d) a demonstration that the tolerable error rate depends strongly on various link and traffic characteristics, thereby implying that a single set of error monitor parameters will not work well in all situations; and (e) some recommendations on a customizable/adaptable scheme of error monitoring with a discussion on their implementability. These issues may be particularly relevant in the presence of anticipated increases in SS7 traffic due to widespread deployment of advanced intelligent network (AIN) and personal communications service (PCS) as well as for developing procedures for high-speed SS7 links currently under consideration by standards bodies     

P-N double quantum well resonant interband tunneling diode withpeak-to-valley current ratio of 144 at room temperature

The current-voltage characteristics of the P-N double quantum well resonant interband tunneling (RIT) diodes in InAlAs-InGaAs system have been improved in this letter. The peak-to-valley current ratio (PVCR) is as high as 144 at room temperature. As we know, this is the highest room temperature PVCR ever reported in any tunneling devices. Moreover, the influence of the central barrier thickness varying from 10 Å to 30 Å on the device characteristics is also studied