A dual front-end for the new GPS/GALILEO generation in a 0.35 μm SiGe process

A highly integrated, low-power GALILEO/GPS front-end for the new generation of positioning services has been designed using a 0.35 μm SiGe process. First an analysis of the current and future GPS and GALILEO signals is presented in order to show the interoperability between both systems and to set the requirements for the entire front-end. The receiver has been implemented using a 6 MHz bandwidth low IF architecture whose IF frequency is 4.092 MHz after digitalization. The ESD protected RF front-end exhibits a voltage gain of 103 dB and an SSB noise figure of 3.7 dB, which makes it suitable for high-sensitivity applications. The achieved power consumption is only 66 mW from a 3 V voltage supply and 38 mW if the internal dual-gain LNA is switched off with no compromise with performance and with a minimal amount of external components.     

Power efficient multi-stage CMOS rectifier design for UHF RFID tags

Power efficiency of a UHF rectifier circuit, which is part of long-range IC-based passive RFID tags, has become a serious bottleneck in implementing power-hungry intelligent sensors. This paper presents an analytical approach for multi-stage rectifiers, which provides design tradeoffs as well as a set of design rules to improve power efficiency of the rectifier. As an example, three-stage rectifiers are designed with ST 90 nm CMOS technology for optimized performance at both 10 and 22 m distances. When compared with existing results at the same level of output power, the proposed rectifiers show a 3× better performance in power efficiency (73%) and 55% reduction in power-up threshold with longer operating range.     

Surface passivation of cadmium zinc telluride radiation detectors by potassium hydroxide solution

The spectral resolution of cadmium zinc telluride (CZT) room temperature nuclear radiation detectors is often limited by the presence of conducting surface species that increase the surface leakage current. Surface passivation plays an important role in reducing this surface leakage current and thereby decreasing the noise of the detectors and improving the spectral energy resolution. Chemical etching with a Br-MeOH solution leaves CZT surfaces rich in Te and is considered as one of the primary causes of the increased surface leakage current. Previous studies have shown that hydrogen peroxide (H₂O₂) forms oxides of tellurium on the CZT surface and thus acts as a good passivating agent. In this study we will present results on the use of potassium hydroxide (KOH) as an alternative passivating agent. The KOH aqueous solution leaves a more stoichiometric (evaluated from the trends in the surface Cd:Te ratio) and smoother CZT surface. The passivation effects of KOH solution on the surface of the CZT have been characterized by current-voltage measurements for different KOH concentrations and etching times for both parallel strip electrodes as well as a metal-semiconductor-metal configuration. The surface chemical composition and its morphology were studied by scanning x-ray photoelectron spectroscopy and atomic force microscopy. The comparison and demonstration of improvements in the spectral resolution of the CZT detectors (based on ²⁴¹Am spectra) with and without the KOH treatment are presented.     

Study of CdSSe:V and CdMnTe:V photorefractive effect

A large photorefractive effect was measured in CdS_0.8Se_0.2:V and Cd_0.55Mn_0.45Te:V ternary crystals which shows promise for many device applications such as optical signal processing and optical limiting. In this study, we compared the results obtained from two-wave mixing experiments with Cd_0.55Mn_0.45Te:V and CdS_0.8Se_0.2:V crystals at the 633 nm wavelength. As the signal to pump beam ratio was varied from 10⁻¹ to 10⁻⁴, Cd_0.55MN_0.45Te:V and CdS_0.8Se_0.2:V showed a maximum photorefractive gain of 0.17 and 0.20 cm⁻¹, respectively. The grating formation time of both the crystals were measured to be in the milli-second range at an incident intensity of 200 mW/cm².     

Stable operation of IEEE 802.11e EDCA: Interaction between offered load and MAC parameters

In this paper, we study impacts of TXOP allocation and AIFS parameter on one hop IEEE 802.11e EDCA network under varying offered load. Offered load is modified by changing the parameters of arrival process and node populations. Arrival process is varied by altering burst size distribution, mean burst size, frame size, and arrival rates. We investigate the effects of the offered load parameters on the network stability and non-saturation boundaries of IEEE 802.11e EDCA. Our results show interaction of offered load and MAC parameters. The results suggest the range of network parameters which preserve network stability and still achieve QoS differentiation.     

Distributed power control algorithm for cognitive radios with primary protection via spectrum sensing under user mobility

Substantial spectrum gains have been demonstrated with the introduction of cognitive radio however; such gains are usually short lived due to the increased level of interference to licensed users of the spectrum. The interference management problem is herein tackled from the transmitter power control perspective so that transmissions by cognitive radio network does not violate the interference threshold levels at the primary users as well as maintain the QoS requirements of cognitive radio users. We model the cognitive radio network for mobile and immobile users and propose algorithms exploiting primary radio environment knowledge (spectrum use), called power control with primary protection via spectrum sensing. The algorithm is briefly introduced for time invariant systems and demonstrated that it has the ability to satisfy tight QoS constraints for cognitive radios as well as meet the interference constraints for licensed users. We, however, further show that such assumption of terminal immobility in the power control algorithm would fail in cases where user mobility is considered, resulting in increased levels of interference to the primary as well as increased outages in cognitive radio network. We model the link gain evolution process as a distance dependent shadow fading process and scale-up the target signal to interference ratio to cope with user mobility. Since mobility driven power control algorithms for cognitive radios have not been investigated before, we therefore, propose a mobility driven power control framework for cognitive radios based on spectrum sensing, which ensures that the interference limit at the primary receiver is unperturbed at all times, while concurrently maintaining the QoS within the cognitive radio network as compared to static user cases. We also corroborate our algorithms with proof of convergence.     

Assembly reliability assessment and life estimation for a stacked area array device

Memory module manufacturers face an ongoing challenge to incorporate more functionality and superior performance with each new generation of product offering. The growth in demand for memory capacity is surpassing the pace at which memory component manufacturers are able to cost-effectively produce the next-generation of monolithic memory devices. Stacking components helps in the transition to higher-density memory while the design and production capability for the next-generation of memory devices is being developed. However, on the other hand, the complex nature of stacked Chip Scale Package (CSP) components mandates a thorough review of the assembly processes and a detailed reliability assessment for these packages.The research objective was to study the assembly reliability of stacked CSP components assembled on a densely populated lead-free memory module utilizing mirror imaged component placements. The assessment was carried out using thermal cycling and mechanical shock tests. The data collected from thermal cycling was also used for failure modeling and life estimation. The methodology for estimating field life was established and the field life was estimated for a server application. The results proved that stacked CSP components can be reliably assembled. The module using stacked CSP components surpassed the life expectancy for server applications, which is 10 years.     

An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth

It is well known that common subexpression elimination techniques minimize the two main cost metrics namely logic operators and logic depths in realizing finite impulse response (FIR) filters. Two classes of common subexpressions occur in the canonic signed digit representation of filter coefficients, called the horizontal and the vertical subexpressions. Previous works have not addressed the trade-offs in using these two types of subexpressions on the logic depth and the number of logic operators of coefficient multipliers. In this paper, we analyze the impact of the horizontal and the vertical common subexpression elimination techniques on reducing the logic depth and number of logic operators in FIR filters. Further, we present an algorithm to optimize the common subexpression elimination that produces FIR filters with fewer numbers of logic operators when compared with other common subexpression elimination algorithms in literature. The design examples show that the average reduction of logic operators achieved using our method over the weight-2 horizontal common subexpression elimination method which produced the best trade-off between logic operators and logic depth (contention resolution algorithm, CRA-2 [F. Xu, C.-H. Chang, C.-C. Jong, Contention resolution algorithm for common subexpression elimination in digital filter design, IEEE Trans. Circuit Syst. II 52(10) (2005) 695-700 (October)]) is 15%. This reduction of logic operators is achieved without any increase in the logic depth. When compared with the recently proposed multiple adder graph (MAG) algorithm [Jeong-Ho Han, In-Cheol Park, FIR filter synthesis considering multiple adder graphs for a coefficient, IEEE Trans. Comput.-Aid. Design Integ. Circuit Syst. 27(5) (2008) 958-962 (May)], the average reduction of logic operators obtained using our method is 5% and the reduction of logic depth is 25%.     

Micro cantilever probe array integrated with Piezoresistive sensor

A micro cantilever-tip silicon probe-array with integrated electro-thermal nano-tip and piezoresistive sensor has been presented for NEMS high-density data storage. After its fundamental working principle has been illustrated, such a 1×10 probe-array has been designed. Both analysis and FEM simulation are used for modeling and designing with their results agreeing well with tolerance of only 5%. The device has been fabricated with silicon bulk micromachining technologies. The relationship between the heating resistance and tip temperature was experimentally obtained and fitted with second order polynomial function. Based on those, the microsecond-instantaneous electro-thermal performance of the device has been gained and the tested results were in agreement with the simulated ones. Under the 4 V pulse power and 3 μs heating time, the tested results were indicative of the 463.15 K temperature on the tip, the 6.2 μs decreasing-temperature constant of the heating resistor and the nearly 100 KHz reading-writing velocity. The sensitivity of piezoresistivity was up to 5.4×10⁴ under the force of 2×10⁻⁷ N, which was sufficient to read out the data from the polymer indent.     

Low-complexity bit-parallel systolic multipliers over GF(2)

This paper presents new time-dependent and time-independent multiplication algorithms over finite fields GF(2^m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithm allows efficient realization of the bit-parallel systolic multipliers. The results show that the proposed time-independent multiplier saves about 54% space complexity as compared to other related multipliers for polynomial and dual bases of GF(2^m). The proposed architectures include the features of regularity, modularity and local interconnection. Accordingly, it is well suited for VLSI implementation.