A lifetime prediction method for hot-carrier degradation insurface-channel p-MOS devices

Hot carrier degradation of p-MOS devices at low gate voltages (V_g<V_d) is examined. It is shown that the electronic gate current is the principal factor in stress damage in this gate voltage range and that the damage itself consists of trapped electrons, localized close to the drain junction. The saturation of the transconductance change as a function of time which is seen at long stress times of high stress voltages results from a change in the injected gate current as a function of time. This is caused by changes in electric field in the silicon due to charge trapping in the oxide during stress. The saturation effect can, however, be transformed into a simple power law if the time axis is multiplied by the square of the instantaneous gate current. This allows for the development of a lifetime-prediction method. The method is applied to 1.0-μm p-MOS devices, and a lifetime is estimated     

Anomalous hot-carrier behavior for LDD p-channel transistors

It has previously been reported that gradual junction p-channel transistors can have shorter lifetimes under hot-carrier stress conditions than abrupt junction devices (see IEEE Trans. Electron Devices, vol. 39, p. 2290-98, 1992). Here, the work is extended to LDD (lightly doped drain) structures. p-MOS hot-carrier effects are examined for deep submicron structures with abrupt and LDD junctions. It is shown that, contrary to the case of n-MOS transistors, the lifetimes for hot-carrier stress of the LDD p-MOS transistors are actually shorter than their abrupt junction counterparts, in the range of LDD dopings examined here. This is explained in terms of two competing mechanisms, gate electronic injection, which decreases for the LDD junctions, and the size of the damage region in the oxide, which increases for the LDD junctions. It is concluded that using LDD-type structures for hot-carrier control does not automatically guarantee longer lifetimes     

Timing verification of dynamic circuits

A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits     

Low- and high-temperature superconducting microwave filters

Stripline and microstrip filters at X-band were designed and fabricated using low- and high-temperature superconductors in quarter-wave, parallel-coupled section configurations. Low-temperature superconducting niobium thin films, deposited on single-crystal sapphire, were used to build to six-pole stripline filters with adjacent passbands and approximately 3 dB crossovers and 1.2% bandwidth. Four- and six-pole microstrip filters were made with in situ epitaxial YBa₂Cu₃O₇ (YBCO) films on LaAlO₃ substrates. All the YBCO filters showed 77 K passbands with clean skirts and high out-of-band rejection. The six-pole filters had adjacent passbands with -28 dB crossovers and 1.5% bandwidth