Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

Ultra-wideband (from DC to 110 GHz) CPW to CPS transition

A new ultra-wideband, low-loss and small-size coplanar waveguide (CPW) to coplanar strip (CPS) transition which can be used from DC to 110 GHz is presented. The proposed transition connects CPW with CPS by the reformed air-bridge. Two ground planes of CPW are tied at their ends by a line and the centre of the line is connected to the ground strip of CPS by another line. Owing to the symmetry of the proposed structure, the currents of two ground planes of CPW are combined with the same phase and transferred to the ground strip of CPS. With height of 3 μm, the signal line of CPW passes over two connecting lines and is connected to the signal strip of CPS. For the back-to-back transition structure, insertion loss <1 dB and return loss >15 dB are obtained from 0.5 to 110 GHz     

Capacitor coupled converter (C3) for high power DCconversion

The bang-bang controlled capacitor coupled converter (C³) is described in this paper. Due to the converter's inherent commutating property, the C³ can accommodate thyristors as well as high-power gate turn-off switches, due to zero-current switching transitions. The zero-current switching is achieved at no current stress increase, therefore, the topology is considered appropriate for high-power processing. DC and small signal AC models are derived for the bang-bang controlled C³, a design procedure is proposed, and simulation results are discussed. Finally, oscillograms from a proof of principle prototype circuit are presented     

Enantioselective oxidation of sulfides with hydrogen peroxide catalyzed by vanadium complex of sterically hindered chiral Schiff bases

Sterically hindered chiral Schiff base ligands 4a-d were prepared from an aldehyde derived from BINOL. The vanadium complexes of the ligands catalyze an efficient, enantioselective H₂O₂-promoted sulfoxidation of alkyl aryl sulfides, and enantioselectivities as high as 98-99% ee are observed in the sulfoxidation of benzyl aryl sulfides.     

Structural reliability assessment of multi-stack package (MSP) under high temperature storage (HTS) testing condition

Wire ball open failure at the interface of the gold wire and bonding pad of a multi-stack package (MSP) under high temperature storage (HTS) condition of 150 °C is studied. Failure analysis using FIB-SEM was conducted by in-plane moiré interferometry and FEA to clarify the failure mechanism. The ball open failure due to Kirkendall void that results from metal diffusion at high temperature was accelerated by the tensile stress imposed at the gold wire. The tensile stress developed at the gold wire when packages showing different warpage behaviours were stacked. Mechanical interaction between top and bottom packages caused unstable warpage, readily twisted and saddled. The wire came in contact with the photo-sensitive solder resist (PSR) dam because of the unstable warpage and this contact resulted in tensile stress at the gold wires. Solder flux residues reacted with the encapsulant, and as a result, the encapsulant of the top package adhered to the chip of the bottom package, and this adherence created additional tensile stress at the gold wires. To reduce the tensile stress at the wires, the PSR dam was removed, loop shape was altered from 45° to 90°, water soluble flux was applied, and cleaning process was added. HTS reliability was significantly improved and guaranteed after reducing the tensile stress at the wires.     

Matrix substitution method for power bus analysis with isolated power island in high-speed packages and PCBs

We propose a matrix substitution method for analyzing a power bus containing a power island in high-speed packages and printed circuit boards (PCBs). The method is based on a segmentation method and a resonant cavity model for a rectangular cavity, and the impedance of the power bus containing the power island can be calculated analytically. Finally, the proposed method is verified by means of impedance measurements in the frequency domain.     

High average power, high repetition rate, picosecond pulsed fiber master oscillator power amplifier source seeded by a gain-switched laser diode at 1060 nm

We demonstrate a pulsed ytterbium-doped fiber master-oscillator power amplifier source at 1060 nm producing over 300 W of average power in 20-ps pulses at 1-GHz repetition rate. The pulses generated by a gain-switched diode were compressed by a chirped fiber Bragg grating and amplified without any distortion with excellent spectral quality. This fiber master oscillator power amplifier system offers versatility and potential for further power scaling.     

High-Performance Al–Sn–Zn–In–O Thin-Film Transistors: Impact of Passivation Layer on Device Stability

We fabricated high-performance thin-film transistors (TFTs) with an amorphous-Al–Sn–Zn–In–O (a-AT-ZIO) channel deposited by cosputtering using a dual Al–Zn–O and In–Sn–O target. The fabricated AT-ZIO TFTs, which feature a bottom-gate and bottom-contact configuration, exhibited a high field-effect mobility of 31.9 $ hbox{cm}^{2}/hbox{V}cdothbox{s}$, an excellent subthreshold gate swing of 0.07 V/decade, and a high $I_{{rm on}/{rm off}}$ ratio of $≫hbox{10}^{9}$, even below the process temperature of 250 $^{circ}hbox{C}$. In addition, we demonstrated that the temperature and bias-induced stability of the bottom-gate TFT structure can significantly be improved by adopting a suitable passivation layer of atomic-layer-deposition-derived $hbox{Al}_{2} hbox{O}_{3}$ thin film.      

Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport

Metal‐assisted chemical etching (MacEtch) has shown tremendous success as an anisotropic wet etching method to produce ultrahigh aspect ratio semiconductor nanowire arrays, where a metal mesh pattern serves as the catalyst. However, producing vertical via arrays using MacEtch, which requires a pattern of discrete metal disks as the catalyst, has often been challenging because of the detouring of individual catalyst disks off the vertical path while descending, especially at submicron scales. Here, the realization of ordered, vertical, and high aspect ratio silicon via arrays by MacEtch is reported, with diameters scaled from 900 all the way down to sub‐100 nm. Systematic variation of the diameter and pitch of the metal catalyst pattern and the etching solution composition allows the extraction of a physical model that, for the first time, clearly reveals the roles of the two fundamental kinetic mechanisms in MacEtch, carrier generation and mass transport. Ordered submicron diameter silicon via arrays with record aspect ratio are produced, which can directly impact the through‐silicon‐via technology, high density storage, photonic crystal membrane, and other related applications.