W-band divide-by-3 frequency divider using 0.1 /spl mu/m InAlAs/InGaAs metamorphic HEMT technology

A W-band divide-by-3 frequency divider with wide bandwidth and low power dissipation is presented using harmonic injection-locking technique. A cascode FET is employed for a self-oscillating second-harmonic mixer which is injection-locked by third-harmonic input to obtain the division order of three. The fabricated frequency divider using 0.1 /spl mu/m GaAs metamorphic HEMT technology shows superior performance such as large bandwidth of 6.1 GHz around 83.1 GHz (7.3%) under small DC power consumption of 12 mW.     

2/spl times/4 optical add-drop module with no difference in propagation length

We developed a micromachined X-type 2/spl times/4 optical add-drop module (OADM) featuring no difference in propagation length. Four pairs of lensed fibers are aligned in "X" position, and four micromirrors are located between the pairs of optical fibers. The OADM was fabricated utilizing a silicon-on-insulator process. Electrostatic comb actuators can be driven up to 90 /spl mu/m to change the light path within 1 ms. The insertion loss and the on-off ratio were less than 3 and 70 dB, respectively. The loss uniformity in every channel was 1.5 dB.     

A 0.6–2.7 GHz Semidynamic Frequency Divide-by-3 Utilizing Wideband RC Polyphase Filter in 0.18 $mu$m CMOS

A wideband complementary metal oxide semiconductor (CMOS) semidynamic frequency divide-by-3 covering more than two octave bandwidths is presented. The wideband operation without requiring a quadrature signal source is realized by employing a three-stage RC polyphase filter. The transfer function analysis on Type-II two- and three-stage polyphase filters is performed to provide analytic solutions of the peak phase error and peak attenuation. Implemented in 0.18 mum CMOS, the divide-by-3 operates over the input frequency range between 0.6 and 2.7 GHz while dissipating 15 mA from a 1.8 V supply.     

Noise–Power Optimization of Incremental Data Converters

Incremental data converters (IDCs) are useful in instrumentation and measurement applications, where low-frequency analog signals need to be converted into digital form with high accuracy and low power dissipation. They are particularly well suited for applications where a single analog-digital converter is multiplexed between many channels. This paper proposes an exact design methodology for IDCs, which optimizes the signal-to-noise ratio of the converter under practical design constraints. The process also allows the designer to apportion the noise budget in an arbitrary manner between thermal and quantization noise. The design process is illustrated by an example which describes the optimization of a third-order multiplexed IDC.     

A boosted voltage generator for low-voltage DRAMs

This paper proposes a new two-stage two-phase VPP charge pump configured in such a manner that the body effect and the threshold voltage loss are eliminated. The newly proposed circuit is fabricated using 0.18 μm triple-well CMOS process and the measurement result shows that the VPP level tracks 3VDD when VDD is above the threshold voltage.     

Performance modeling and evaluation of data/voice services in wireless networks

Application-level performance is a key to the adoption and success of the CDMA 2000. To predict this performance in advance, a detailed end-to-end simulation model of a CDMA network is built to include application traffic characteristics, network architecture, network element details using the proposed simulation methodology. We assess the user-perceived application performance when a RAN and a CN adopt different transport architectures such as ATM and IP. To evaluate the user-perceived quality of voice service, we compare the end-to-end packet delay for different vocoder schemes such as G.711, G.726 (PCM), G.726 (ADPCM), and vocoder bypass scheme. By the simulation results, the vocoder bypass scenario shows 30% performance improvement over the others. We also compare the quality of voice service with and without DPS scheduling scheme. We know that DPS scheme keep the voice delay bound even if the service traffic is high. For data packet performance, HTTP v.1.1 shows better performance than that of HTTP v.1.0 due to the pipelining and TCP persistent connection. We may conclude that IP transport technology is better solution for higher FER environment since the packet overhead of IP is smaller than that of ATM for web browsing data traffic, while it shows opposite effect to the small size voice packet in RAN architecture. We show that the 3G-1X EV-DO system gives much better packet delay performance than 3G-1X RTT. The main conclusion is that end-to-end application-level performance is affected by various elements and layers of the network and thus it must be considered in all phases of the development process. Jae-Hyun Kim He received the B.S., M.S., and Ph.D. degrees, all in computer science and engineering, from Hanyang University, Ansan, Korea, in 1991, 1993, and 1996 respectively. In 1996, he was with the Communication Research Laboratory, Tokyo, Japan, as a Visiting Scholar. From April 1997 to October 1998, he was a post-doctoral fellow at the department of electrical engineering, University of California, Los Angeles. From November 1998 to February 2003, he worked as a member of technical staff in Performance Modeling and QoS management department, Bell laboratories, Lucent Technologies, Holmdel, NJ. He has been with the department of electrical engineering, Ajou University, Suwon, Korea, as an assistant professor since 2003. His research interests include QoS issues and cross layer optimization for high-speed wireless communication. Dr. Kim was the recipient of the LGIC Thesis Prize and Samsung Human-Tech Thesis Prize in 1993 and 1997, respectively. He is a member of the Korean Institute of Communication Sciences (KICS), Korea Institute of Telematics and Electronis (KITE), Korea Information Science Society (KISS), and IEEE. Hyun-Jin Lee received the B.S. degree in electrical engineering from Ajou University, Suwon, Korea, in 2004, and is working toward the M.S. degree and Ph. D. degree in electrical engineering at Ajou University. He has been awarded Samsung Human-Tech Thesis Prize in 2004. His research interests QoS, especially network optimization and wireless packet scheduling. He is a member of the KICS. Sung-Min Oh received the B.S. and M. S. degrees in electrical engineering form Ajou University, Suwon, Korea, in 2004, and is working toward the Ph. D. degree in electrical engineering at Ajou University. His research interests QoS performance analysis and 4G network. He is a member of the KICS. Sung-Hyun Cho received his B.S., M.S., and Ph.D. in computer science and engineering from Hanyang University, Korea, in 1995, 1997, and 2001, respectively. From 2001 to 2005, he has been with Samsung Advanced Institute of Technology, where he has been engaged in the design and standardization of MAC and upper layers of B3G, IEEE 802.16e, and WiBro systems. He is currently a MAC part leader in the telecommunication R&D center of Samsung Electronics. His research interests include 4G air interface design, radio resource management, cross layer design, and handoff in wireless systems.     

Five Novel Taccalonolides from the Roots of the Vietnamese Plant Tacca paxiana

Chemical investigation of the roots of the Vietnamese plant Tacca paxiana resulted in the isolation of five new steroidal compounds, taccalonolide R ( 6 ), S ( 7 ), T ( 8 ), U ( 9 ), and V ( 10 ). Their structures were established on the basis of NMR and mass‐spectral data. In addition, the five known taccalonolides A ( 1 ), B ( 2 ), E ( 3 ), K ( 4 ), and N ( 5 ) were also isolated and identified.     

Rapid DNA hybridization analysis using a PDMS microfluidic sensor and a molecular beacon.

A rapid DNA analysis has been developed based on a fluorescence intensity change of a molecular beacon in a PDMS microfluidic channel. Recently, we reported a new analytical method of DNA hybridization involving a PDMS microfluidic sensor using fluorescence energy transfer (FRET). However, there are some limitations in its application to real DNA samples because the target DNA must be labelled with a suitable fluorescent dye. To resolve this problem, we have developed a new DNA microfluidic sensor using a molecular beacon. By monitoring the change in the restored fluorescence intensity along the channel length, it is possible to rapidly detect any hybridization of the molecular beacon to the target DNA. In this case, the target DNA does not need to be labelled. Our experimental results demonstrate that this microfluidic sensor using a molecular beacon is a promising diagnostic tool for rapid DNA hybridization analysis.     

Collision-Free Interleaver Composed of a Latin Square for Parallel-Architecture Turbo Codes

In parallel-architecture turbo codes, the constituent interleavers must avoid memory collision. This paper proposes a collision-free interleaver structure composed of a Latin square (LS) and pre-designed interleavers. Our proposed interleavers can be easily optimized for various information block sizes and for various degrees of parallelism. Their performances were evaluated by computer simulation.