Investigation of organic impurities adsorbed on and incorporated into electroplated copper layers

At room temperature electroplated copper layers exhibit changes in resistivity, residual stress, and microstructure. This process, known as self-annealing, is intimately linked to the release of organic impurities, which stem from the incorporation of organic additives into the Cu layer in the course of the electroplating process. The behavior of these impurities during self-annealing, represented by the carbon content, could be detected by analytical radio frequency glow discharge optical emission spectrometry (GD-OES) and carrier gas hot extraction (CGHE). The precondition of a quantitative determination is a surface cleaning procedure to remove adsorbed organics from the copper surface. It was observed that at first almost all impurities have to leave the Cu metallization before an accelerated abnormal grain growth can start. The small amount of remaining organic species after self-annealing could be quantified by both examination techniques, GD-OES and CGHE.     

Rietveld refinement of CdSe phases annealed under argon atmosphere

Hexagonal and cubic cadmium selenide were prepared from a chemical route by using cadmium chloride and potassium selenium hydride obtained from reaction of selenium powder and potassium boron hydride. The product obtained was thermally treated under argon flux at 300, 500 and 600 °C for 2 h and characterized by X-ray photoelectron spectroscopy and X-ray diffraction. The X-ray diffraction data were refined by Rietveld method and the structural parameters were determined for the phases of each annealed samples. At 300 °C five phases were identified: Cubic and hexagonal cadmium selenides and the contaminants: Potassium chloride, boron oxide and cadmium boron oxide. At 500 and 600 °C only the hexagonal cadmium selenide phase was identified besides the other above mentioned contaminant.     

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.     

Diagnosis and Consulting for Control Network Performance Engineering of CSMA-Based Networks

Network performance engineering can verify the design and dimensioning of large-scale control networks like CSMA-based building automation networks. It combines performance analysis with diagnosis methods to evaluate the network utilization and to detect design errors before installation and can therewith save the expenses of overdimensioning and redesign. This paper will develop a diagnosis model based on fault trees that is able to use the huge amount of performance analysis results to identify design errors and analyze their coherences. This enables not only a fast tracing back of fault causes and the derivation of solutions; it can also visualize the fault coherence to the user and help him to understand his design. Additional consulting tools implement best practice strategies, to support the user in parameterization.