Fiber-optic devices for local area network application

Recent developments on fiber-optic devices are reviewed from the local area network (LAN) application viewpoint. Future technical trends are also discussed, along with current research activities. In local area network systems, low device cost and easy maintenance or maintenance-free devices are especially required. Light sources and photodetectors suitable for the systems are described. InGaAsP/InP light emitting diodes can cover a broad application field, up to a gigabits per second super high-speed network region. Optical passive devices, which include branching couplers, switches and connectors, are mentioned as essential components. Compact transmitter/receiver module technology is a key factor in realizing optical-fiber local area network systems. An example of 200-Mbit/s transmitter/receiver module is reported.     

On Critical Stability of Three Quantum Charges Interacting Through Delta Potentials

We consider three one-dimensional quantum, charged and spinless particles interacting through delta potentials. We derive sufficient conditions which guarantee the existence of at least one bound state.     

Polygonal approximation for image segmentation

A new learning model for real-time, grey-level image segmentation is presented. The model gives excellent results for images with different shapes.     

Integrated-optic device for a fibre laser Doppler velocimeter

We first demonstrate an integrated-optic device for a fibre laser Doppler velocimeter, which consists of a waveguide interferometer and a frequency shifter in z-propagation Ti-diffused LiNbO3. The device is also pigtailed with a single-mode fibre to pick up a Doppler-shifted signal. Using the fabricated device, the velocity of a moving object was successfully heterodyne-detected with a signal/noise ratio of 30dB.     

A Graphene Field-Effect Device

In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs     

Breakdown behavior of GaAs/AlGaAs HBTs

Avalanche breakdown behavior at the collector junction of the GaAs/AlGaAs HBT (heterojunction bipolar transistor) has been studied. Junction breakdown characteristics displaying hard breakdown, soft breakdown, and negative resistance breakdown behavior were observed and are interpreted by analysis of localized microplasma effects, uniform microplasma-free behavior, and associated current gain measurements. Light emission from the collector-base junction of the GaAs/AlGaAs HBT was observed and used to investigate breakdown uniformity. Using a simple punchthrough breakdown model, the theoretical breakdown curves at different collector doping concentrations and thicknesses were computed and found to be in agreement with maximum breakdown voltages measured from devices displaying the most uniform junction breakdown. The serious current gain degradation of GaAs/AlGaAs HBTs at low current densities was analyzed in connection with the measurement of a large collector-emitter breakdown voltage. The unexpected functional relationship between the collector-emitter breakdown voltage and collector-base breakdown voltage is explained by the absence of a hole-feedback effect for devices not exhibiting transistor action     

Maximization of Good Chips Per Wafer by Optimization of Memory Redundancy

In the optimization of the number of good chips per wafer, yield is obviously one key factor. It plays the major role in the manufacturing phase, as at this time circuit design and chip area cannot be modified. In the design phase, however, chip area as the second factor defining good chips per wafer can still be influenced. If there are no strong relationships between yield and chip area, both can be optimized independently. In some cases, however, there are such strong relationships, and an optimum of yield gain versus area growth has to be found. Maybe the most important example where strong relationships between area and yield have to be considered is the estimation of optimum memory redundancy. In this paper, we will review and discuss relationships between yield and area and present methods for optimization of good chips per wafer, with special focus on the optimization of memory redundancy     

Microprocessor testability

As the level of microprocessor complexity increases to several hundred thousand transistors for a single-chip machine, it is becoming very difficult to test commercially available designs to the level of fault coverage desired by some customers. In order to achieve near 100-percent coverage of single stuck-at faults, future microprocessors must be designed with special testing features (designed for testability). The authors describe the testing problem for microprocessors, including the various methods of generating test sets and their application by the user. A survey of the testability features of some of today's commercially available microprocessors is presented. Suggestions for testability features for future-generation microprocessors are also discussed