A posteriori error analysis of a quadratic finite volume method for nonlinear elliptic problems

In this article, we construct and analyze a residual-based a posteriori error estimator for a quadratic finite volume method (FVM) for solving nonlinear elliptic partial differential equations with homogeneous Dirichlet boundary conditions. We shall prove that the a posteriori error estimator yields the global upper and local lower bounds for the norm error of the FVM. So that the a posteriori error estimator is equivalent to the true error in a certain sense. Numerical experiments are performed to illustrate the theoretical results.     

变频调速技术在定量包装机中的应用

介绍一种基于变频调速控制的全自动定量包装机，结构简单，组态灵活，性价比高，可广泛应用于食品饲料等行业，现场运行实践证明其通用性好，准确度和可靠性高、速度快、稳定性好。并论述变频器控制系统的设计及使用中的注意问题。     

Performance study of iSCSI-based storage subsystems

iISCSI is emerging as an end-to-end protocol for transporting storage I/O block data over IP networks. By exploiting the ubiquitous Internet infrastructure, iSCSI greatly facilitates remote storage, remote backup, and data mirroring. This article evaluates the performance of two typical iSCSI storage subsystems by measuring and analyzing block-level I/O access performance and file-level access performance. In the file-level performance study, we compare file access performance in an NAS scheme with that in an iSCSI-based SAN scheme. Our test results show that Gigabit Ethernet-based iSCSI can reach very high bandwidth, close to that of a direct FC disk access in block I/O access. However, when the iSCSI traverses through longer distance, throughput relies heavily on the available bandwidth between the initiator and the target. On the other hand, the file-level performance shows that iSCSI-based file access (SAN scheme) provides higher performance than using NFS protocol in Linux and SMB protocol in Windows (NAS scheme). However, the advantage of using iSCSI-based file accesses decreases as the file size increases. The obtained experimental results shed some light on the performance of applications based on iSCSI storage.     

Optimum Design for RF Windows in Millimeter Wave High Power Tubes

The pill-box and block RF windows for millimeter wave (MMW) tubes are presented. The pill-box window is suitable for broadband MMW tubes. And the block window can be used for high power tubes in short MMW. The equivalent circuits for two windows are given. To reach better match characteristics in wider operating bandwidth, the optimum design methods for pill-box and block window in MMW tubes are described in this paper. The testing results show that the theoretic computation is fast and useful accuracy. The design methods possess references value to designer for MMW tubes.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

Popular biorthogonal wavelet filters via a lifting scheme and its application in image compression

A technique using a lifting scheme is presented for constructing compactly supported wavelets whose coefficients are composed of free variables locating in an interval. An efficient approach-based wavelet for image compression is developed by selecting the coefficients of the 9-7 wavelet filter and associated lifting scheme. Furthermore, the rationalised coefficients wavelet filter that can be implemented with simple integer arithmetic is achieved and its characteristic is close to the well known original irrational coefficients 9-7 wavelet filters developed by A. Cohen et al. (Commun. Pure Appl. Maths., vol.45, no.1, p.485-560, 1992). To reduce the computational cost of image coding applications further, an acceleration technique is proposed for the lifting steps. Software and hardware simulations show that the new method has very low complexity, and simultaneously preserves the high quality of the compressed image.     

差分跳频通信系统的特点及性能

文章介绍了一种新型的短波跳频通信技术——差分跳频,分析了差分跳频技术区别于常规跳频技术的主要特点。针对按序列检测的信号接收方法,对差分跳频通信系统在AWGN信道下的性能进行了理论分析,同时做出相应的计算机仿真,证实了差分跳频通信技术和按序列检测方法的结合,使通信系统在AWGN信道下的性能得到了比较显著的提升。     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

一种高精度的非平稳随机信号实时建模算法研究

针对传统的非平稳随机信号时变参数筹分模型算法的不足,论文把非平稳随机信号时变参数差分模型与一种带自适应遗忘因子的RLS算法结合起来,形成一种有效的非平稳随机信号实时建模算法,仿真分析表明该算法不仅能获得快的收敛速度而且能获得高的建模精度。