Lipase‐Supported Metal–Organic Framework Bioreactor Catalyzes Warfarin Synthesis

A green and sustainable strategy synthesizes clinical medicine warfarin anticoagulant by using lipase‐supported metal–organic framework (MOF) bioreactors (see scheme). These findings may be beneficial for future studies in the industrial production of chemical, pharmaceutical, and agrochemical precursors.     

Comprehensive Profiling by Non-targeted Stable Isotope Tracing Capillary Electrophoresis-Mass Spectrometry: A New Tool Complementing Metabolomic Analyses of Polar Metabolites

Mass spectrometry (MS) driven metabolomics is a frequently used tool in various areas of life sciences; however, the analysis of polar metabolites is less commonly included. In general, metabolomic analyses lead to the detection of the total amount of all covered metabolites. This is currently a major limitation with respect to metabolites showing high turnover rates, but no changes in their concentration. Such metabolites and pathways could be crucial metabolic nodes (e.g., potential drug targets in cancer metabolism). A stable-isotope tracing capillary electrophoresis–mass spectrometry (CE-MS) metabolomic approach was developed to cover both polar metabolites and isotopologues in a non-targeted way. An in-house developed software enables high throughput processing of complex multidimensional data. The practicability is demonstrated analyzing [U-¹³C]-glucose exposed prostate cancer and non-cancer cells. This CE-MS-driven analytical strategy complements polar metabolite profiles through isotopologue labeling patterns, thereby improving not only the metabolomic coverage, but also the understanding of metabolism.     

A new strategy for synthesis of branched cyclic peptide by Asn side-chain hydrazide ligation

Here, we report a new strategy for rapid synthesis of branched peptide by side-chain hydrazide ligation at Asn. The hydrazide was converted to thioester at Asn side chain by NaNO₂ and thiol reagent, and sequential ligation with an N-terminus Cys-peptide efficiently afforded the branched peptide. A branched cyclic peptide was successfully synthesized by side-chain ligation with a two-Cys-peptide and formation of a disulfide bond. This approach provides a new way for expeditious synthesis of branched peptides and facilitates the design of neopeptides as functional bio-mimics.     

Et2Zn-mediated stoichiometric C(sp)-H silylation of 1-alkynes and chlorosilanes

A first example of an Et₂Zn mediated silylation of 1-aklynes is reported. A series of functional groups are tolerated in this reaction. Mechanistic studies support Zn alkynilides as intermediates in the reaction. This reaction protocol provides a practical method for the preparation of alkynylsilanes and expands the application of organometallic zinc in organic synthesis.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.