Symbol rate and modulation level-controlled adaptivemodulation/TDMA/TDD system for high-bit-rate wireless data transmission

This paper proposes a time-division multiple-access/time-division duplex (TDMA/TDD)-based symbol rate and modulation level-controlled adaptive modulation system for high-bit-rate data transmission. The proposed system controls both the symbol rate and modulation level for the next transmission time slot according to the estimated carrier power to noise spectral density ratio (C/N₀) and delay spread for the time slot to achieve higher bit rate and higher transmission quality as well as higher delay-spread immunity. It is demonstrated by computer simulation and laboratory experiments that the proposed system can achieve a higher average bit rate with higher transmission quality in comparison with the fixed-rate quaternary phase-shift keying (QPSK) system and modulation level-controlled adaptive modulation system in both flat Rayleigh and frequency-selective fading environments. The simulated and experimental results also show that the proposed adaptive modulation techniques can be applied to 1-2-Mb/s indoor and outdoor microcellular systems with its delay spread of up to 250 ns and its terminal mobility of up to pedestrian speed without employing any special antifrequency-selective fading techniques, such as the adaptive equalizer and space diversity     

Communication network protocol for real-time distributed controland its LSI implementation

A new token-passing mechanism, priority token passing, which features real-time access and fast detection and recovery of transmission errors, is discussed in detail in comparison with standard token-passing protocols, and its large-scale integration (LSI)-oriented design concept is described. Priority token passing includes only a small performance overhead, due to its switching functions, which can change network topology from ring to broadcast medium. A token-holding node passes the token to another node after determining the successor through priority comparison. Errors occurring during token passing can, thus, be detected and corrected simply and promptly. Priority token passing has a simple hardware implementation, requiring only small additions to the frame control circuitry, and has a small implementation overhead. The priority token-passing protocol and two other important network communication functions, dual ring network reconfiguration and high-level data link control (HDLC) normal response mode-based message transmission, are designed as a single finite-state machine, and implemented into a compact LSI chip. This integrated instrument network (IINET) chip provides complete network communication services and requires only three additional external electronic components for operation     

A tutorial on wavelets from an electrical engineering perspective.I. Discrete wavelet techniques

The objective of this paper is to present the subject of wavelets from a filter-theory perspective, which is quite familiar to electrical engineers. Such a presentation provides both physical and mathematical insights into the problem. It is shown that taking the discrete wavelet transform of a function is equivalent to filtering it by a bank of constant-Q filters, the non-overlapping bandwidths of which differ by an octave. The discrete wavelets are presented, and a recipe is provided for generating such entities. One of the goals of this tutorial is to illustrate how the wavelet decomposition is carried out, starting from the fundamentals, and how the scaling functions and wavelets are generated from the filter-theory perspective. Examples (including image compression) are presented to illustrate the class of problems for which the discrete wavelet techniques are ideally suited. It is interesting to note that it is not necessary to generate the wavelets or the scaling functions in order to implement the discrete wavelet transform. Finally, it is shown how wavelet techniques can be used to solve operator/matrix equations. It is shown that the “orthogonal-transform property” of the discrete wavelet techniques does not hold in numerical computations     

A novel method for elimination of line-current harmonics insingle-stage PFC switching regulators

This paper studies a particular single-stage power-factor-correction (PFC) switching regulator employing a discontinuous-conduction-mode (DCM) boost-input cell and a continuous-current-mode (CCM) forward output cell. Although this single-stage PFC regulator can provide a reasonably high power factor when its PFC stage is operating in discontinuous mode, substantial reduction in line-current harmonics is possible by applying a suitable frequency-modulation scheme. This paper derives a frequency-modulation scheme and proposes a practical implementation using a simple translinear analog circuit. A quantitative analysis on the total harmonic distortion (THD) of the line current when the circuit is subject to a limited range of frequency variations is presented along with some considerations for practical design. Experimental data obtained from a prototype confirms the effectiveness of the proposed frequency-modulation scheme. The proposed analog translinear circuit allows custom integrated circuit implementation, making it a viable low-cost solution to the elimination of line-current harmonics in switching regulators     

Parallel, self-organizing, hierarchical neural networks. II

For pt.I see IEEE Trans. Neural Networks, vol.1, p.167-78 (1990). Parallel, self-organizing, hierarchical neural networks (PSHNNs) involve a number of stages with error detection at the end of each stage, i.e., rejection of error-causing vectors, which are then fed into the next stage after a nonlinear transformation. The stages operate in parallel during testing. Statistical properties and the mechanisms of vector rejection of the PSHNN are discussed in comparison to the maximum likelihood method and the backpropagation network. The PSHNN is highly fault tolerant and robust against errors in the weight values due to the adjustment of the error detection bounds to compensate errors in the weight values. These properties are exploited to develop architectures for programmable implementations in which the programmable parts are reduced to on-off or bipolar switching operations for bulk computations and attenuators for pointwise operations     

Spatial retardation of carrier heating in scaled 0.1-μmn-MOSFET's using Monte Carlo simulations

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V_d considerably less than the Si/SiO₂ injection barrier height φ_b. Simulation of both devices reveal that 1) although qV_d<φ_b, carriers can obtain energies greater than φ_b, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates     

Packed hyper-ellipsoid classifiers

Pattern classification is frequently performed using the k-nn algorithm or a neural network. The choice of parameters for the former is often difficult and the amount of data which has to be stored in the classifier can be high. Neural network classifiers can overcome some of these problems but learning is often unreliable and slow. An alternative which combines some of the best features of the k-nn and neural network classifier is described by the authors. The classifier is called a packed hyper-ellipsoid classifier     

Interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd0.96Zn0.04 Te (211)B substrates by molecular beam epitaxy

Double-crystal x-ray rocking curve (DCRC) and secondary-ion mass-spectroscopy (SIMS) measurements have been performed to investigate the effect of rapid thermal annealing on the interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd_0.96Zn_0.04Te (211)B substrates by molecular beam epitaxy. The sharp satellite peaks of the DCRC measurements on a 100-period HgTe/CdTe (100Å/100Å) superlattice show a periodic arrangement of the superlattice with high-quality interfaces. The negative direction of the entropy change obtained from the diffusion coefficients as a function of the reciprocal of the temperature after RTA indicates that the Hg diffusion for the annealed HgTe/CdTe superlattice is caused by an interstitial mechanism. The Cd and the Hg concentration profiles near the annealed HgTe/CdTe superlattice interfaces, as measured by SIMS, show a nonlinear behavior for Hg, originating from the interstitial diffusion mechanism of the Hg composition. These results indicate that a nonlinear interdiffusion behavior is dominant for HgTe/CdTe superlattices annealed at 190°C and that the rectangular shape of HgTe/CdTe superlattices may change to a parabolic shape because of the intermixing of Hg and Cd due to the thermal treatment.     

Performance analysis of an improved MMSE multiuser receiver formismatched delay channels

Motivated by the fact that time delays in a practical direct-sequence code-division multiple-access (DS-CDMA) system can never be perfectly estimated, an improved minimum-mean squared-error (MMSE)-based receiver is proposed and analyzed. Via the simple assumption of a probability distribution for the delay estimation errors, the proposed receiver can achieve a performance superior to that of the conventional MMSE (CMMSE) receiver. The performances of this improved receiver and the CMMSE receiver are compared in terms of the mean squared error (MSE), probability of error, and asymptotic multiuser efficiency (AME). As the original definition of AME does not consider mismatched channels, the behavior of three single-user receivers bearing imperfect delay estimation is also investigated. These single-user receivers are employed to define a more appropriate AME. Finally, an efficient update mechanism to accommodate dynamic channel statistics, and thus practical implementation, is proposed     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications