K0.9Li0.1（Ta0.5Nb0.5）O3晶体压电应变系数的测量

用准静态ｄ＿（３３）测量仪和干涉法相结合。测量了Ｋ＿（０．９）Ｌｉ＿（０．１）（Ｔａ＿（０．５）Ｎｂ＿（０．５）Ｎｂ＿（０．５））Ｏ＿３晶体的压电应变系数。结果为：ｄ＿（３３）＝８６．０，ｄ＿（３３）＝一２９．５，ｄ＿（１５）＝１１２．９×１０￣（－１２）Ｃ／Ｎ．     

混沌电路同步的研究

本文叙述对混沌电路实现同步控制的实验研究之初步结果。所用的电路为蔡氏电路和锁相环电路。这项研究工作在通信系统中有应用前景。     

Nd：MgO：LiNbO3晶体的荧光光谱及其双晶体腔内互倍频实验

采用激光感生荧光技术测量了Ｎｄ：ＭｇＯ：ＬｉＮｂＯ３晶体的偏振荧光光谱，简要地说明了Ｎｄ：ＭｇＯ：ＬｉＮｂＯ３双晶体腔内互倍频的基本原理，并在实验中用染料激光作泵浦源实现了其双晶体腔内互倍频运转；得到５４３ｎｍ横模倍频绿光单端输出约ＹＭＷ，腔前泵浦阈值约３８ＭＷ，总转换效率约为１．３％。     

利用空间多普勒调谐技术冷却原子及其速度单一化

本文理论计算了用圆锥管内多次全反射激光而产生的多普勒频移来冷却原子束的机制。给出了最佳冷却原子束的圆锥管的夹角、长度、反射次数及激光入、出射角等参数。理论计算了原子束经过圆锥管冷却的速度分布情况。数值计算结果表明：采用两个长１３０ｃｍ的锥形管来冷却原子束，选用合适的失谐量可使极大部分速度小于１２００ｍ／ｓ的原子冷却到８ｌｍ／ｓ，并且可得到单一速度的高亮度的原子束。     

Protocol design and performance analysis for manufacturing messagespecification: A Petri net approach

The manufacturing message specification (MMS) is the ISO standard communication protocol specific to manufacturing. To analyze MMS design and performance, service unit automats are introduced to represent individual MMS services, while service connection Petri Nets (PNs) are constructed from these automats to describe MMS service connections and processes. This approach makes MMS protocol specification and analysis possible in terms of well-developed concepts and methods in PN theory. It leads to a distributed and hierarchical model of MMS software system by integrating service connection PNs. A generalized stochastic PN for MMS performance evaluation is obtained by incorporating service parameters and time factors into the model. A technique based on T-invariants is used to simplify the performance analysis     

Turbo multiuser detection with unknown interferers

We consider the problem of turbo multiuser detection for synchronous and asynchronous code-division multiple-access (CDMA) in the presence of unknown users. Turbo multiuser detectors, as previously developed, typically require knowledge of the signature waveforms of all of the users in the system and ignore users whose signature sequences are unknown, e.g., users outside the cell. We develop turbo multiuser detection for CDMA uplink systems and other environments in which the receiver has knowledge of the signature waveforms of only K˘⩽ K users. Subspace techniques are used to estimate the interference from the unknown-users and the interference estimate is subtracted from the received signal. We see that the new receiver significantly outperforms the conventional turbo multiuser receiver for moderate and high signal-to-noise ratios. It is also seen that the traditional turbo receiver provides little gain through iteration when unknown users are present     

Ka-band solid-state pulsed Gunn oscillator and power combiner

GaAs Gunn diodes were fabricated for pulse source application at 8 mm wave band and operated with pulsewidths of 0.05 to 2.0 microseconds and duty cycles of 0.001 to 0.01. Peak pulse output power levels of 0.8–1.2W are achieved and the maximum available power is 1.6W with the highest efficiency of 6.5 percent. A simple and compact pulsed power combiner is also given in this paper.     

7.5 Gb/s monolithically integrated clock recovery circuit using PLLand 0.3-μm gate length quantum well HEMT's

A monolithically integrated clock recovery (CR) circuit making use of the phase-locked loop (PLL) circuit technique and enhancement/depletion AlGaAs/GaAs quantum well-high electron mobility transistors (QW-HEMT's) with gate lengths of 0.3 μm has been realized. A novel preprocessing circuit was used. In the PLL a fully-balanced varactorless VCO was applied. The VCO has a center oscillating frequency of about 7.7 GHz and a tuning range greater than 500 MHz. A satisfactory clock signal has been obtained at a bit rate of about 7.5 Gb/s. The power consumption is less than 200 mW at a supply voltage of -5 V     

New efficient designs for XOR and XNOR functions on the transistorlevel

Two new methods are proposed to implement the exclusive-OR and exclusive-NOR functions on the transistor level. The first method uses non-complementary signal inputs and the least number of transistors. The other one improves the performance of the prior method but two more transistors are utilized. Both of them have been fully simulated by HSPICE on a SUN SPARC 2 workstation     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states