Control system design on a power-split CVT for high-power agricultural tractors

The problem considered in this paper is the design and tuning of the control system of a power-split continuously variable transmission (CVT) used in high-power tractors. Power-split CVTs are characterized by the combination of a traditional mechanical transmission and by a continuously-variable transmission. This guarantees, at the same time, smooth variations of the transmission-ratio and high efficiency of the overall transmission system. The control architecture of an hydrostatic power-split CVT is constituted by three main parts: 1) servo-controller on the current of the valve which drives the hydraulic transmission; 2) a servo-controller on the hydraulic transmission-ratio; and 3) a synchronizer which coordinates the hydraulic and the mechanical parts of the CVT. In this work, these three controllers are fully developed, including: design, implementation, and evaluation on an experimental system.     

On-demand learning for a wireless campus

The current Internet and wireless networks are harsh environments for transporting high-bandwidth multimedia data. We examine the technical issues involved, and describe an end-to-end solution to support a Web-based learn-on-demand system that operates in a wireless campus environment.     

Relevance of coupling effects on DRA array design

A finite-difference time-domain (FDTD) approach is proposed in order to obtain suitable criteria for the design of a four-element dielectric resonator antenna (DRA) array. The numerical analysis is focused on the study of the electromagnetic coupling phenomena arising between DRA fed by a microstrip-slot transition. Scattering parameters behavior and radiation patterns are determined by taking advantage of the geometrical symmetry of the structure, analyzing only one half or one quarter of the entire domain through two or four separate FDTD runs.     

Full-diversity, high-rate space-time block codes from division algebras

We present some general techniques for constructing full-rank, minimal-delay, rate at least one space-time block codes (STBCs) over a variety of signal sets for arbitrary number of transmit antennas using commutative division algebras (field extensions) as well as using noncommutative division algebras of the rational field /spl Qopf/ embedded in matrix rings. The first half of the paper deals with constructions using field extensions of /spl Qopf/. Working with cyclotomic field extensions, we construct several families of STBCs over a wide range of signal sets that are of full rank, minimal delay, and rate at least one appropriate for any number of transmit antennas. We study the coding gain and capacity of these codes. Using transcendental extensions we construct arbitrary rate codes that are full rank for arbitrary number of antennas. We also present a method of constructing STBCs using noncyclotomic field extensions. In the later half of the paper, we discuss two ways of embedding noncommutative division algebras into matrices: left regular representation, and representation over maximal cyclic subfields. The 4/spl times/4 real orthogonal design is obtained by the left regular representation of quaternions. Alamouti's (1998) code is just a special case of the construction using representation over maximal cyclic subfields and we observe certain algebraic uniqueness characteristics of it. Also, we discuss a general principle for constructing cyclic division algebras using the nth root of a transcendental element and study the capacity of the STBCs obtained from this construction. Another family of cyclic division algebras discovered by Brauer (1933) is discussed and several examples of STBCs derived from each of these constructions are presented.     

The extended quadratic residue code is the only (48,24,12) self-dual doubly-even code

An extremal self-dual doubly-even binary (n,k,d) code has a minimum weight d=4/spl lfloor/n/24/spl rfloor/+4. Of such codes with length divisible by 24, the Golay code is the only (24,12,8) code, the extended quadratic residue code is the only known (48,24,12) code, and there is no known (72,36,16) code. One may partition the search for a (48,24,12) self-dual doubly-even code into three cases. A previous search assuming one of the cases found only the extended quadratic residue code. We examine the remaining two cases. Separate searches assuming each of the remaining cases found no codes and thus the extended quadratic residue code is the only doubly-even self-dual (48,24,12) code.     

PNNI-based control plane for automatically switched optical networks

Much effort has been spent on the definition of control plane protocols for automatically switched optical networks (ASON). Most of the proposals brought into the standardization for an International Telecommunications Union-Telecommunication Sector, Internet Engineering Task Force, and Optical Internetworking Forum are based on Internet protocol concepts. One such proposal is the generalized multi-protocol label switching (GMPLS), an extension of the MPLS traffic engineering control plane model that includes nonpacket switched technologies (time, wavelength, and fiber switching). Recently, the potential use of private network-network interface (PNNI) in ASONs has been discussed as an alternative proposal by the standardization bodies. The goal of this paper is to appropriately adapt asynchronous transfer mode into an optical PNNI (O-PNNI) protocol that can be used as the control plane of ASONs. The paper also provides a critical viewpoint on the potential usage of either O-PNNI or GMPLS control plane and analyzes the pros and cons of each. The methodology adopted toward devising O-PNNI hinges on reviewing PNNI along with ASON recommendations in order to determine the set of PNNI features that require adaptation. Having identified these features we engineer and present appropriate solutions relating to routing, signaling and addressing aspects.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Application of extended boundary conditions and the Haar wavelets in the analysis of wave scattering by thin screens

A recent approach to solution of 2D scattering problems for electromagnetic waves scattered by thin screens is analyzed. With the use of examples of scattering by a strip and an unclosed cylindrical surface, it is shown that the proposed approach has no advantages in terms of the efficiency of numerical solution over a well-known approach based on exact integral equations for currents that have singular kernels and that are solved with the Krylov-Bogoliubov method.     

Routing Correlated Data with Fusion Cost in Wireless Sensor Networks

In this paper, we propose a routing algorithm called minimum fusion Steiner tree (MFST) for energy efficient data gathering with aggregation (fusion) in wireless sensor networks. Different from existing schemes, MFST not only optimizes over the data transmission cost, but also incorporates the cost for data fusion, which can be significant for emerging sensor networks with vectorial data and/or security requirements. By employing a randomized algorithm that allows fusion points to be chosen according to the nodes' data amounts, MFST achieves an approximation ratio of 5/4log(k + 1), where k denotes the number of source nodes, to the optimal solution for extremely general system setups, provided that fusion cost and data aggregation are nondecreasing against the total input data. Consequently, in contrast to algorithms that only excel in full or nonaggregation scenarios without considering fusion cost, MFST can thrive in a wide range of applications     

Sigma-delta modulators operating at a limit cycle

A new type of sigma-delta modulator that operates in a special mode named limit-cycle mode (LCM) is proposed. In this mode, most of the SDM building blocks operate at a frequency that is an integer fraction of the applied sampling frequency. That brings several very attractive advantages: a reduction of the required power consumption per converted bandwidth, an immunity to excessive loop delays and to digital-analog converter waveform asymmetry and a higher tolerance to clock imperfections. The LCMs are studied via a graphical application of the describing function theory. A second-order continuous time SDM with 5 MHz conversion bandwidth, 1 GHz sampling frequency and 125 MHz limit-cycle frequency is used as a test case for the evaluation of the performance of the proposed type of modulators. High level and transistor simulations are presented and compared with the traditional SDM designs.