Allocation heuristics and defragmentation measures for reconfigurable systems management

A novel technique is proposed for the management of a 2D reconfigurable device in order to get true hardware multitasking. We use a Vertex List Set to keep track of the free area boundary. This structure contains the best candidate locations for the task, and several heuristics are proposed to select one of them, based in fragmentation and adjacency. A Look-Ahead heuristic that anticipates the next known event is also proposed. A metric is used to estimate the fragmentation status of the FPGA, based on the number of holes and their shape. Defragmentation measures are taken when needed.     

Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study

This work presents a detailed case study in customizing a configurable, extensible, 32-bit RISC processor with vector/SIMD instruction extensions for the efficient execution of block-based video-coding algorithms utilizing a proprietary co-design environment. In addition to the default Full-Search motion estimation of the MPEG-2 Test Model 5, fourteen fast ME algorithms were implemented in both scalar and vector form. Results demonstrate a reduction of up to 68% in the dynamic instruction count of the full search-based encoder whereas the fast motion estimation algorithms achieved a reduction in instruction count of nearly 90%, both accelerated via three 128-bit vector/SIMD instructions when compared to the scalar, reference implementation of the standard. We address in detail the profiling, vectorization and the development of these vector instruction set extensions, discuss in depth the implementation of a parametric vector accelerator that implements these instructions and show the introduction of that accelerator into a 32-bit RISC processor pipeline, in a closely-coupled configuration.