Analogue switch for very low-voltage applications

A new analogue switch suitable for operation at very low-voltage supply in a standard CMOS technology is presented. The proposed switch is based on 'quasi-floating-gate' transistors and has a simple and compact structure. For illustrative purposes, two sample-and-hold circuits operating from a single supply voltage close to the threshold voltage of a transistor, and using the proposed technique, are presented. Experimental results obtained from prototypes in a 1.5 /spl mu/m CMOS technology are provided.     

Algebraic theory of optimal filterbanks

We introduce an optimality theory for finite impulse response (FIR) filterbanks using a general algebraic point of view. We consider an admissible set /spl Lscr/ of FIR filterbanks and use scalability as the main notion based on which performance of the elements in /spl Lscr/are compared. We show that quantification of scalability leads naturally to a partial ordering on the set /spl Lscr/. An optimal solution is, therefore, represented by the greatest element in /spl Lscr/. It turns out that a greatest element does not necessarily exist in /spl Lscr/. Hence, one has to settle with one of the maximal elements that exist in /spl Lscr/. We provide a systematic way of finding a maximal element by embedding the partial ordering at hand in a total ordering. This is done by using a special class of order-preserving functions known as Schur-convex. There is, however, a price to pay for achieving a total ordering: there are infinitely many possible choices for Schur-convex functions, and the optimal solution specified in /spl Lscr/ depends on this (subjective) choice. An interesting aspect of the presented algebraic theory is that the connection between several concepts, namely, principal component filterbanks (PCFBs), filterbanks with maximum coding gain, and filterbanks with good scalability, is clearly revealed. We show that these are simply associated with different extremal elements of the partial ordering induced on /spl Lscr/ by scalability.     

Super-multi-fibre PLC connector utilising angled connection between PLC and tens of fibres

A novel super-multi-fibre planar lightwave circuit (PLC) connector, designed to connect tens of optical fibres and a PLC for super-multichannel PLC-based optical modules with a receptacle interface, is proposed. This connector employs an angled connection instead of a PC connection. A 0.127 mm pitch 32-fibre connector is also demonstrated, which exhibits low connection and high return losses.     

Colloidal processing of polymer ceramic nanocomposite integral capacitors

Polymer ceramic composites form a suitable material system for low temperature fabrication of embedded capacitors appropriate for the MCM-L technology. Improved electrical properties such as permittivity can be achieved by efficient filling of polymers with high dielectric constant ceramic powders such as lead magnesium niobate-lead titanate (PMN-PT) and barium titanate (BT). Photodefinable epoxies as the matrix polymer allow fine feature definition of the capacitor elements by conventional lithography techniques. The optimum weight percent of dispersant is tuned by monitoring the viscosity of the suspension. The dispersion mechanism (steric and electrostatic contribution) in a slightly polar solvent such as propylene glycol methyl ether acetate (PGMEA) is investigated from electrophoretic measurements. A high positive zeta potential is observed in the suspension, which suggests a strong contribution of electrostatic stabilization. By optimizing the particle packing using a bimodal distribution and modified processing methodology, a dielectric constant greater than 135 was achieved in PMN-PT/epoxy system. Suspensions are made with the lowest PGMEA content to ensure the efficiency of the dispersion and efficient particle packing in the dried film. Improved colloidal processing of nanoparticle-filled epoxy is a promising method to obtain ultra-thin capacitor films (<2/spl mu/m) with high capacitance density and improved yield. Capacitance of 35 nF/cm/sup 2/ was achieved with the thinnest films (2.5-3.0 /spl mu/m).     

Fractal-wavelet image denoising revisited.

The essence of fractal image denoising is to predict the fractal code of a noiseless image from its noisy observation. From the predicted fractal code, one can generate an estimate of the original image. We show how well fractal-wavelet denoising predicts parent wavelet subtress of the noiseless image. The performance of various fractal-wavelet denoising schemes (e.g., fixed partitioning, quadtree partitioning) is compared to that of some standard wavelet thresholding methods. We also examine the use of cycle spinning in fractal-based image denoising for the purpose enhancing the denoised estimates. Our experimental results show that these fractal-based image denoising methods are quite competitive with standard wavelet thresholding methods for image denoising. Finally, we compare the performance of the pixel- and wavelet-based fractal denoising schemes.     

The X<Superscript>+</Superscript> trion in a system with spatial separation of the charge carriers

A system composed of two heavy holes located in a two-dimensional (2D) quantum well (QW) and bound via mediation of an electron in a neighboring 2D QW is considered. Using a simple qualitative trial wave function, the ground-state energy of this kind of X⁺ trion is determined in the infinite-hole-mass approximation as a function of the QW spacing. Coordinate dependence of the effective potential binding the holes to each other is calculated for different values of QW spacing. In the adiabatic approximation, a set of dependences describing the X⁺ trion binding energy as a function of the electron mass to the hole mass ratio is obtained. Several estimates for the trion binding energy in GaAs-and ZnSe-based double-QW heterostructures are given.     

A printer model using signal processing techniques

An accurate printer model that is efficient enough to be used by halftoning algorithms is proposed. The proposed signal processing model (SPM) utilizes a physical model to train adaptive linear combiners (ALCs), after which the average exposure of each subpixel for any input pattern can be calculated using the optimized weight vector. The SPM can be used to model multi-level halftoning and resolution enhancement, as well as traditional halftoning. The SPM is comprised of a single ALC layer followed by a peak-to-average ratio (PAR) correction layer, which serves to produce a PAR of less than 1.5 in the modeled exposure. The PCN (PAR correction network) employs one ALC/pixel and exploits the physics governing the characteristics of exposure in small regions. A relatively small number of training patterns suffices to train the SPM.     

Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

Improved-performance noncoherent weighted-coefficients diversity combiner for DPSK and NC-FSK signals in nonidentical Nakagami fading channels

It is well-known that noncoherent equal-gain combining (NC-EGC) is the simplest combining technique for noncoherent and differentially coherent communication systems. However, for nonidentical Nakagami-m channels (channels having nonuniform multipath intensity profile (MIP) and/or arbitrary non-integer fading parameters), the use of NC-EGC has three main disadvantages. First, its performance serves as a lossy upper bound to that of the optimum diversity combiner. Second, it results in complicated expressions for the system average error performance. Third, it incurs noncoherent combining loss (does not aid the use of diversity) at relatively low average signal-to-noise ratio (SNR). In this letter, we propose a modified version of the NC-EGC, which is a noncoherent combiner with weighting coefficients, to overcome the disadvantages of the conventional one. We show that this alternative combiner does provide improvements over the conventional N.C-EGC for all values of average SNRs, it does not incur any noncoherent combining loss, and it leads to a design of the receiver whose average error performance can be evaluated easily.     

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented