Multidimensional DSP Core Synthesis for FPGA

Current rapid synthesis approaches for reusable dedicated hardware components (cores) for digital signal processing systems are ineffective since they fail to capture and exploit the manner in which the resulting components are used as part of a heterogeneous system. This leads to counter-productive core redesign for each use of the core. This paper presents a solution to this issue which combines a novel but intuitive system modeling technique and associated core generation and integration methodology which generates reuable core architectures which may be optimised via algorithm level transformations. For an example design problem, these provide an effective rapid core synthesis and implementation exploration flow which allows a factor 3.9 throughput increase with no extra hardware expense. John McAllister received a first honours B.Eng degree in Electrical and Electronic Engineering and the degree of PhD from Queen’s University Belfast, UK in 2001 and 2004 respectively.From October 2004 to July 2005 he was a Postdoctoral Research Assistant in the Programmable Systems Laboratory in the System on Chip research group in the Institute for Electronics, Communication and Information Technology (ECIT) at Queen’s University Belfast.In July 2005 he was appointed to a lectureship in SoC technology in the International Centre for System-on-Chip and Advanced Microwireless (SoCAM) project at ECIT. Roger Woods received the degree of B.Sc with Honours in Electrical and Electronic Engineering and degree of Ph.D. from the Queen’s University of Belfast, UK in 1985 and 1990 respectively. From 2003, he has been a Professor at the same university and leads the programmable systems and networks laboratory there. His main research interests are programmable hardware systems using FPGAs, design tools for heterogeneous platforms and low power VLSI. He has published over 120 papers in the area of VLSI and DSP, holds two patents and serves on numerous technical program committees including Workshop on Signal Processing Systems, Field Programmable Logic and Field Programmable Technology. He is a member the IEEE Signal Processing Society Technical Committee for the Design and Implementation of Signal Processing Systems and chair of the IEE Professional Network on Microelectronics and Embedded Systems. Richard Walke received his Ph.D. from Warwick University in 1998 for work on arithmetic, architectures and implementations of adaptive weight calculation in ASIC. Subsequently he worked on the implementation of a range of DSP algorithms in FPGA, specialising in floating-point arithmetic, digital receivers and adaptive beamformers on FPGA. In recent years he has lead work to address the design of heterogeneous systems employing both processor and FPGA. Last year he moved to Xilinx, and is now responsible for the development of their floating-point IP solution. Darren Reilly received first honours B.Eng. Degree in Electronic and Software Engineering from the Queen’s University Belfast in 2002. He is currently pursuing a Ph.D. in Queen’s University Belfast due to finish in September 2005. His research interests lie in the rapid development of efficient architectures for FPGA as part of a system level design flow.     

Certain Relations on the Congruence Lattice of a Completely Regular Semigroup

   Communicated by     

Some conditions related to the exactness of Rees-Sushkevich varieties

This article presents some conditions, expressed in terms of the inclusion and exclusion of certain small semigroups, that are related to a Rees-Sushkevich variety being generated by completely 0-simple or completely simple semigroups.     

Molecular Modeling of Two Disaccharides Containing Fructopyranose Linked to Glucopyranose

Abstract

Ramachandran energy surfaces for the disaccharides leucrose and turanose were computed using MM3. For each molecule, thirty-two combinations of hydroxyl and primary alcohol group orientations were considered. The calculations used a dielectric constant of 4.0 and the maps were generated on a 20° grid-spacing. The models compared well with the corresponding crystal structures except for significant deviations in some of the anomeric C-O bond lengths.     

The impacts of speed-to-market on new product success: the moderating effects of uncertainty

Time-based strategy is becoming an important weapon to achieve competitive advantage in the current environment of fast-changing technology and customer requirements. Speed-to-market has become the mantra of both researchers and practitioners in new product development (NPD), but there are limited and conflicting findings on the relationship between speed-to-market and product success. A more important question is whether faster is always better. In a study of 692 NPD projects, we examined the relationship between speed-to-market and new product success (NPS) under different conditions of uncertainty. Our results indicate that speed-to-market is generally positively associated with overall NPS, but market uncertainty moderates the direct effect. Speed-to-market is less important to NPS under conditions of low market uncertainty. Our results also suggest that technological uncertainty does not affect the speed-success relationship. The implication is that it is more important to execute a time-based strategy in an unfamiliar, emerging, or fast-changing market than in a familiar, existing, and stable market. The limitations and future research related to these results are discussed.     

Comments, with reply, on 'A real-time high-resolution technique for angle-of-arrival estimation' by J.P. Reilly

See ibid. vol.75, no.12, p.1692-4 (Dec. 1987). The commenters explain why they disagree with some assertions in the above-titled letter and point out some omissions that they consider important. In particular, they maintain the systolic array of W.M. Gentleman and H.T. Kung cannot be used for subspace estimation in high-resolution methods. The author points out some alternative interpretations that present the original work in a different light.<>     

Resource allocation planning helper (ralph): Lessons learned

The Jet Propulsion Laboratory's (JPL) Resource Allocation Process incorporated the decision-making software system RALPH into the planning process four years ago. The principal task of the Resource Allocation Process includes the planning and apportionment of JPL's Ground Data System composed of the Deep Space Network and Mission Control and Computing Center facilities. The addition of the data-driven, rule-based planning system, RALPH, has expanded the planning horizon from eight weeks to 10 years and has resulted in significant labor savings. Use of the system has also resulted in important improvements in science return through enhanced resource utilization. In addition, RALPH has been instrumental in supporting rapid turn around for an increased volume of special “what if” studies.

This paper reviews the status of RALPH and focuses on important lessons learned from the creation of a highly functional design team, through an evolutionary design and implementation period, and through the fundamental changes to the process that spawned the tool kit. Principal topics include proper integration of software tools within the planning environment, transition from prototype to delivered software, changes in the planning methodology as a result of evolving software capabilities, and creation of the ability to develop and process generic requirements to allow planning flexibility.     

Finding fixed satellite service orbital allotments with ak-permutation algorithm

A satellite system synthesis problem, the satellite location problem (SLP), is addressed. In SLP, orbital locations (longitudes) are allotted to geostationary satellites in the fixed satellite service. A linear mixed-integer programming model is presented that views SLP as a combination of two problems: the problem of ordering the satellites and the problem of locating the satellites given some ordering. A special-purpose heuristic procedure, a k-permutation algorithm, that has been developed to find solutions to SLPs formulated in the manner suggested is described. Solutions to small example problems are presented and analyzed on the basis of calculated interferences