Study of the self-alignment of no-flow underfill for micro-BGA assembly

As a concept to achieve high throughput low cost flip-chip assembly, a process development activity is underway, implementing next generation flip-chip processing based on large area underfill printing/dispensing, IC placement, and simultaneous solder interconnect reflow and underfill cure. The self-alignment of micro-BGA (ball grid array, BGA) package using flux and two types of no-flow underfill is discussed in this paper. A “rapid ramp” temperature profile is optimized for reflow of micro-BGA using no-flow underfill for self-aligning and soldering. The effect of bonding force on the self-alignment is also described. A SOFTEX real time X-ray inspection system was used to inspect samples to ensure the correct misalignment before reflow, and determine the residual displacement of solder joints after reflow. Cross-sections of the micro-BGA samples are taken using scanning electronic microscope. Our experimental results show that the self-alignment of micro-BGA using flux is very good even though the initial misalignment was greater than 50% from the pad center. When using no-flow underfill, the self-alignment is inferior to that of using flux. However, for a misalignment of no larger than 25% from the pad center, the package is also able to self-align with S1 no-flow underfill. However, when the misalignment is 37.5–50% from the pad center, there are 10–14% residual displacement after reflow. The reason is the underfill resistant force inhibiting the self-alignment of the package due to rapid increment of underfill viscosity during reflow. The self-alignment of micro-BGA package using no-flow underfill allows only <25% misalignment prior to the soldering. During assembling, although the bonding force does not influence on the self-alignment of no-flow underfill, a threshold bonding force is necessary to make all solder balls contact with PCB pads, for good soldering. The no-flow underfill is necessary to modify the fluxing/curing chemistry for overcoming the effect of tin metal salt produced during soldering on underfill curing, and for maintaining the low viscosity during soldering to help self-alignment.     

Cognitive amplify‐and‐forward relay networks with beamforming under primary user power constraint over Nakagami‐m fading channels

In this paper, we analyze the performance of cognitive amplify‐and‐forward (AF) relay networks with beamforming under the peak interference power constraint of the primary user (PU). We focus on the scenario that beamforming is applied at the multi‐antenna secondary transmitter and receiver. Also, the secondary relay network operates in channel state information‐assisted AF mode, and the signals undergo independent Nakagami‐m fading. In particular, closed‐form expressions for the outage probability and symbol error rate (SER) of the considered network over Nakagami‐m fading are presented. More importantly, asymptotic closed‐form expressions for the outage probability and SER are derived. These tractable closed‐form expressions for the network performance readily enable us to evaluate and examine the impact of network parameters on the system performance. Specifically, the impact of the number of antennas, the fading severity parameters, the channel mean powers, and the peak interference power is addressed. The asymptotic analysis manifests that the peak interference power constraint imposed on the secondary relay network has no effect on the diversity gain. However, the coding gain is affected by the fading parameters of the links from the primary receiver to the secondary relay network. Copyright © 2012 John Wiley & Sons, Ltd.     

Room-Temperature Quantum Cascade Laser: ZnO/Zn1−x Mg x O Versus GaN/Al x Ga1−x N

A ZnO/Zn_1?x Mg _x O-based quantum cascade laser (QCL) is proposed as a candidate for generation of THz radiation at room temperature. The structural and material properties, field dependence of the THz lasing frequency, and generated power are reported for a resonant phonon ZnO/Zn_0.95Mg_0.05O QCL emitting at 5.27 THz. The theoretical results are compared with those from GaN/Al _x Ga_1?x N QCLs of similar geometry. Higher calculated optical output powers [ $ {P}_{\rm{ZnMgO}} $  = 2.89 mW (nonpolar) at 5.27 THz and 2.75 mW (polar) at 4.93 THz] are obtained with the ZnO/Zn_0.95Mg_0.05O structure as compared with GaN/Al_0.05Ga_0.95N QCLs [ $ {P}_{\rm{AlGaN}} $  = 2.37 mW (nonpolar) at 4.67 THz and 2.29 mW (polar) at 4.52 THz]. Furthermore, a higher wall-plug efficiency (WPE) is obtained for ZnO/ZnMgO QCLs [24.61% (nonpolar) and 23.12% (polar)] when compared with GaN/AlGaN structures [14.11% (nonpolar) and 13.87% (polar)]. These results show that ZnO/ZnMgO material is optimally suited for THz QCLs.     

Influence of quantum capture and tunneling mechanisms on the dark current of bound-to-continuum quantum-well infrared photodetectors

We present a theoretical model for the dark current of bound-to-continuum quantum-well infrared photodetectors (QWIPs), by considering the field-induced mixing effect, tunneling rate and phonon scattering rate between bound and continuum states. Using this model, we can see clearly how these mechanisms significantly influence the Fermi levels of bound and continuum electrons, and thus, the dark current. Nonlinear temperature dependence of the dark current at low temperature is predicted and discussed in detail. The simulated dark currents exhibit good agreement with the experimental results, without use of parameter fitting techniques.     

Modal Analysis of Microstrip Antenna on Fiber Reinforced Anisotropic Substrates

In this communication, microstrip antenna on fiber reinforced anisotropic substrates has been considered in aerospace applications; however, the antenna's optical axis may not necessarily be colinear with any of the substrate's principal axes and that leads to a nondiagonal permittivity matrix (tensor). This work extends the studies of microstrip antenna on isotropic substrate and on uniaxial substrate to analyze antenna performance on fiber reinforced anisotropic substrates, where the permittivity matrix has five dielectric constants because of the substrate's fiber direction. The solution is based on modal analysis so that the wave immittance can be derived in a closed form. Analyses and experimental verification show that the antenna performance is strongly influenced not only by the permittivity along the principal axes but also by the fiber direction of the substrate.     

Stability Analysis of a Second Harmonic Coaxial-Waveguide Gyrotron Backward-Wave Oscillator

This study analyzes the stability of a Ka-band second harmonic gyrotron backward-wave oscillator (gyro-BWO) with a coaxial interaction waveguide. All of the possible competing modes in the frequency tuning range are considered. To suppress various competing modes, the downstream part of the coaxial interaction waveguide is loaded with distributed losses. Although the competing modes have different kinds of transverse field distributions, simulation results show that the losses of the outer cylinder and those of the inner cylinder serve as complementary means of suppressing the competing modes. The losses can stabilize the competing modes while having minor effects on the start-oscillation current of the operating mode. Detailed investigations were performed involving the dependence of the start-oscillation currents on the parameters of the lossy inner cylinder and the lossy outer cylinder, including the resistivity and the length of the lossy section. Moreover, under stable operating conditions, the performances of the second harmonic coaxial gyro-BWO with different sets of circuit parameters are predicted and compared.     

Bit-level systolic arrays for modular multiplication

This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S–N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w–2, wherew=n/2. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.     

Quadrature Oscillators with Grounded Capacitors and Resistors Using FDCCIIs

Two current‐mode and/or voltage‐mode quadrature oscillator circuits each using one fully‐differential second‐generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current‐mode quadrature signals have the advantage of high‐output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current‐mode and voltage‐mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.     

Total Power Optimization for Combinational Logic Using Genetic Algorithms

Power consumption is a top priority in high performance circuit design today. Many low power techniques have been proposed to tackle the ever serious, highly pressing power consumption problem, which is composed of both dynamic and static power in the nanometer era. The static power consumption nowadays receives even more attention than that of dynamic power consumption when technology scales below 100 nm. In order to mitigate the aggressive power consumption, various existing low power techniques are often used; however, they are often applied independently or combined with two or at most three different techniques together, and that is not sufficient to address the escalating power issue. In this paper, we present a power optimization framework for the minimization of total power consumption in combinational logic through multiple V _dd assignment, multiple V _th assignment, device sizing, and stack forcing, while maintaining performance requirements. These four power reduction techniques are properly encoded into the genetic algorithm and evaluated simultaneously. The overhead imposed by the insertion of level converters is also taken into account. The effectiveness of each power reduction mechanism is verified, as are the combinations of different approaches. Experimental results are presented for a number of 65 nm benchmark circuits that span typical circuit topologies, including inverter chains, SRAM decoders, multiplier, and a 32 bit carry adder. Our experiments show that the combination of four low power techniques is the effective way to achieve low power budget. The framework is general and can be easily extended to include other design-time low power techniques, such as multiple gate length or multiple gate oxide thickness.     

Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design

Temperature affects not only the performance but also the power, reliability, and cost of the embedded system. This paper proposes a temperature-aware task allocation and scheduling algorithm for MPSoC embedded systems. Thermal-aware heuristics are developed, and a temperature-aware floorplanning tool is used to reduce the peak temperature and achieve a thermally even distribution while meeting real time constraints. The paper investigates both power-aware and thermal-aware approaches to the task allocation and scheduling. The experimental results show that the thermal-aware approach outperforms the power-aware schemes in terms of maximal and average temperature reductions. To the best of our knowledge, this is the first MPSoC task allocation and scheduling algorithm that takes temperature into consideration.

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