Robust vector control of induction motors using full-order observer in consideration of core loss

This paper proposes a method for designing a robust full-order observer for vector-controlled induction motors taking core loss into account. Although conventional research focuses on parameter identification, global stability of the identification remains questionable. Therefore, robustness against some parameters is required. This paper describes the design of a robust full-order observer which takes core loss into account, using both the gain-scheduled H/sub /spl infin// control and the linear matrix inequality technique. This design always results in a stable controller. The robustness of the proposed method against variations of resistances is evaluated by experiments.     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.     

Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

Lateral ion implant straggle and mask proximity effect

Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.     

Vector coupled-mode theory of dielectric waveguides

A consistent derivation of a system of vector coupled-mode (VCM) equations for parallel dielectric waveguides is presented and compared with earlier versions of the improved coupled-mode theory (ICMT). As a validity test, it is shown that the effectively scalar transverse electric and transverse magnetic (TM) coupled-mode (CM) equations are direct limits of our full VCM formulation. In particular, our formulation does not lead to the fundamental error found with earlier coupled-mode theories (CMTs) in a case of TM fields. Functional equations of our VCMT are consistent with Maxwell's equations and lead to higher precision. They can be applied to complicated arrays of strongly coupled parallel dielectric waveguides with true vectorial behavior.     

RLS-based initialization for per-tone equalizers in DMT receivers

Per-tone equalization has recently been proposed as an alternative receiver structure for discrete multitone-based systems improving upon the well-known structure based on time-domain equalization. Fast initialization of all the equalizer coefficients has been identified as an open problem. In this letter, a recursive initialization scheme based on recursive least squares with inverse updating is presented for the per-tone equalizers. Simulation results show convergence with an acceptably small number of training symbols. Complexity calculations are made for per-tone equalization and for the case where tones are grouped. It is demonstrated with an example that in the latter case, initialization complexity becomes sufficiently low and comparable to complexity during data transmission.     

Reducing CIC filter complexity

This paper provides several tricks to reduce the complexity and enhance the usefulness of cascaded integrator-comb (CIC) filters. The first trick shows a way to reduce the number of adders and delay elements in a multi-stage CIC interpolation filter. The result is a multiplierless scheme that performs high-order linear interpolation using CIC filters. The second trick shows a way to eliminate the integrators from CIC decimation filters. The benefit is the elimination of unpleasant data word growth problems.     

Degree-of-polarization and eye-closure penalty associated with optical signals with orthogonal polarizations

We perform a systematic measurement of the degree-of-polarization (DOP) and eye-closure penalty for optical signals with orthogonal polarizations. We find that the symmetry of DOP is maintained for the orthogonal polarizations under both first and higher order polarization-mode dispersion (PMD), whereas the symmetry of eye-closure penalty is broken under second-order PMD. An orthogonal polarization pair can have large disparity of eye-closure penalty despite an identical DOP. We also demonstrate a novel approach to estimate the maximum eye-closure penalty asymmetry with three orthogonal polarizations on the Poincare/spl acute/ sphere.     

Dispersion-tolerant 10-gb/s duobinary system employing heterodyne detection and MLSE

We experimentally demonstrate a 10.7-Gb/s duobinary transmission system operating over a chromatic-dispersion range of /spl sim/12 000 ps/nm. Heterodyne detection and maximum-likelihood sequence estimation are employed to achieve this result.     

Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived and a reduced-complexity algorithm is developed for computation of the proposed computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for the computation of these transforms using the common-core algorithm. The proposed scheme not only leads to a systolic-like regular and modular hardware for computing these transforms, but also offers significant improvement in area-time efficiency over the existing structures. The structure proposed here is devoid of complicated input/output mapping and does not involve any complex control. Unlike the convolution-based structures, it does not restrict the transform length to be a prime or multiple of prime and can be utilized as a reusable core for cost-effective, memory-efficient, high-throughput implementation of either of these transforms