On optimal ordering of signals in parallel wire bundles

Optimal ordering and sizing of wires in a constrained-width interconnect bundle are studied in this paper. It is shown that among all possible orderings of signal wires, a monotonic order of the signals according to their effective driver resistance yields the smallest weighted average delay. Minimizing weighted average delay is a good approximation for MinMax delay optimization. Three variants of monotonic ordering are proven to be optimal, depending on the Miller coupling factors (MCF) ratio between the signals at the sides of the bundle and that of the internal wires. The monotonic order property holds for a very broad range of VLSI circuit settings arising in common design practice. A simple, yet near-optimal, setting of wire widths within the bundle to yield the best average weighted delay is proposed. The theoretical results have been validated by numerical experiments on 65 nm process technology and industrial design data. In all cases the ordering optimization yielded improvement in the range of 10% in wire delay, translated to about 5% improvement in the clock cycle of a high-performance microprocessor implemented in that technology.     

The characterization of semiconductor layer and interface quality with special reference to raman spectroscopy

This article gives a survey over the application of Raman spectroscopy (inelastic light scattering) for the characterization of semiconductor heterostructures, considering the quality of epitaxial layers and their interfaces. Theoretical considerations of Raman scattering are briefly reviewed. Experimental results are presented for various systems of III–V and II–VI compounds. Aspects of interest are crystalline quality, strain, composition of mixed compounds, chemical reactions at interfaces, doping efficiency and implications of interface quality for electronic properties.     

Benefits of chemical beam epitaxy for micro and optoelectronic applications

This paper reviews the benefits that Chemical Beam Epitaxy (CBE) growth technique can bring to micro and optoelectronic devices. The characteristics of the technique are first underlined for a better understanding of the specific advantages it offers compared to other growth techniques. The first one is the low growth temperature, which pushed the thickness limit in strained InGaAsP multi-quantum well structures. Carbon doping of GaAs and In_0.53Ga_0.47As, and its application to GaAs and InP based npn heterojunction bipolar transistors is another important contribution of CBE which has resulted in successful device development. The last developments in surface cleaning and in situ etching with new amine and chloride sources are presented. The capabilities of CBE for selective and uniform growth on partially masked substrates are illustrated through examples of device planarization and integration. Finally, the most recent improvements in the technology of CBE equipment and their impact on CBE production capabilities are presented.     

Photochromism of diarylethene: Effect of polymer environment and effects on surfaces

A diarylethene (DAE) study using thermodynamical physical chemistry, elemental fractal analysis, and quantum chemistry is presented. Attention is focused on the ways the polymer environment affects DAE photochromism and on the ways that DAE photochromism affects surfaces. Non-constant quantum yields in single-molecule measurements, selective metal deposition, and a super-water-repellent fractal surface are discussed after a short summary of the latest experimental results concerning photochromism in DAE molecules.     

Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration

As IC fabrication technologies get into nanometer era, clock routing gradually dominates chip performance indicated by delay, cost, and power consumption. X-architecture can be applied for routing metal wires in diagonal and rectilinear directions to overcome the above challenges due to wirelength reduction. In this paper, we present a clock routing algorithm, called PMXF, to construct an X-architecture zero-skew clock tree with minimum delay. An X-pattern library is defined for simplifying the merging procedure of the DME approach, an X-Flip technique is proposed for reducing the wirelength between the paired points, and a wire sizing technique is applied for achieving zero skew. In terms of clock delay, wirelength, power consumption, and via count listed in the experimental results on benchmarks, the proposed PMXF algorithm can respectively achieve more reductions compared with other previous X-architecture clock routing algorithms.     

Test data compression using alternating variable run-length code

This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases.     

StarPlace: A new analytic method for FPGA placement

To date, the best algorithms for performing placement on Field-Programmable Gate Arrays (FPGAs) are based on Simulated Annealing (SA). Unfortunately, these algorithms are not scalable due to the long convergence time of the latter. With an aim towards developing a scalable FPGA placer we present an analytic placement method based on a near-linear net model, called star+. The star+ model is a variant of the well-known star model and is continuously differentiable - a requirement of analytic methods that rely on the existence of first- and second-order derivatives. Most importantly, with the star+ model incremental changes in cost resulting from block movement can be computed in O(1) time, regardless of the size of the net. This makes it possible to construct time-efficient solution methods based on conjugate gradient and successive over-relaxation for solving the resulting non-linear equation system. When compared to VPR, the current state-of-the-art placer based on SA, our analytic method is able to obtain an 8-9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its fast mode.     

Statistical lifetime reliability optimization considering joint effect of process variation and aging

Aging effect degrades circuit performance in the runtime, interacts with fabrication-induced device parameter variation, and thus posing significant impact on circuit lifetime reliability. In this work, a statistical circuit optimization flow is proposed to ensure lifetime reliability of the manufactured chip in the presence of process variation and aging effects. It exploits a variation-aware gate-level statistical aging degradation model to characterize circuit lifetime reliability, identifies a set of worst duty cycles on the inputs of statistically critical gates to estimate the worst delay degradations on these gates. Based on the delay degradation information, statistical gate sizing is performed which enables the manufactured chip to satisfy lifetime reliability constraint in term of low area overhead.