Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs

Signal through-the-silicon via (STS-via) planning plays an important role in multi-layer nets which need vertical interconnection between different device layers. Moreover, STS-via can also dissipate heat, which is a much more serious problem in 3D ICs than in 2D ICs. Since the through-the-silicon via is large and can only be inserted into whitespace of the device layer, planning STS-via for thermal optimization may affect the interconnection wire length. Therefore, in order to make STS-via planning more flexible, we integrated STS-via with pin assignment. In this paper, we use min-cost maximum flow algorithm for STS-via planning and pin assignment simultaneously. Experimental results show that our approach can reduce both temperature and wire length effectively with short runtime.     

Performance of two-hop infrastructure based multi-antenna regenerative relaying in Rayleigh fading channel

Cooperative relaying is considered as an effective technique to enlarge the coverage area and enhance the system capacity for the future wireless systems. In this paper, an infrastructure based multi-antenna cooperative relay network has been investigated. Closed form expressions of outage probability and average error rate have been derived, when the relay and the destination perform selection combining of the signals. The relay is assumed to operate in the adaptive decode and forward mode. The effect of number of antennas installed on the relay and their placement has also been studied.     

Reputation-based network selection mechanism using game theory

Current and future wireless environments are based on the coexistence of multiple networks supported by various access technologies deployed by different operators. As wireless network deployments increase, their usage is also experiencing a significant growth. In this heterogeneous multi-technology multi-application multi-terminal multi-user environment users will be able to freely connect to any of the available access technologies. Network selection mechanisms will be required in order to keep mobile users “always best connected” anywhere and anytime. In such a heterogeneous environment, game theory techniques can be adopted in order to understand and model competitive or cooperative scenarios between rational decision makers. In this work we propose a theoretical framework for combining reputation-based systems, game theory and network selection mechanism. We define a network reputation factor which reflects the network’s previous behaviour in assuring service guarantees to the user. Using the repeated Prisoner’s Dilemma game, we model the user–network interaction as a cooperative game and we show that by defining incentives for cooperation and disincentives against defecting on service guarantees, repeated interaction sustains cooperation.     

Enhanced mobility and environmental stability in all organic field‐effect transistors: The role of high dipole moment solvent

Low‐operating voltage, high mobility, and stable organic field‐effect transistors (OFETs) using polymeric dielectrics such as pristine poly(4‐vinyl phenol) (PVP) and poly(methyl methacrylate) (PMMA), dissolved in solvents of high dipole moment, have been achieved. High dipole moment solvents such as propylene carbonate and dimethyl sulfoxide used for dissolving the polymer dielectric enhance the charge carrier mobilities by three orders of magnitude in pentacene OFETs compared with low dipole moment solvents. Fast switching circuits with patterned gate PVP‐based pentacene OFETs demonstrated a switching frequency of 75 kHz at input voltages of |5 V|. The frequency response of the OFETs is attributed to a high degree of dipolar‐order in dielectric films obtained from high‐polarity solvents and the resulting energetically ordered landscape for transport. Remarkably, these pentacene‐based OFETs exhibited high stability under bias stress and in air with negligible shifts in the threshold voltage. © 2013 Wiley Periodicals, Inc. J. Polym. Sci., Part B: Polym. Phys. 2013 , 51, 1533–1542     

An automated high-level topology generation procedure for continuous-time ΣΔ modulator

This paper presents an automated procedure for generation of high-level topologies for continuous-time ΣΔ modulator system. A functional topology of the system is generated from the given transfer function model of the modulator. Mathematical transformation technique is applied iteratively over the initial topology to generate a functional topology which is optimized for modulator sensitivity, hardware complexity and relative power consumption. This is then implemented using behavioral models of operational transconductance amplifiers and capacitors. The generated high-level topology is ensured to work with reasonable accuracy under non-ideal conditions. The entire procedure has been implemented in Matlab/Simulink environment. Numerical results have been provided to demonstrate the procedure.     

A pre-placement individual net length estimation model and an application for modern circuits

With the advances in integrated circuit (IC) technology, managing the individual and total interconnect is becoming one of the main challenges facing designers. An individual a-priori length estimation model can be a useful tool in helping designers obtain lower net lengths and congestion of interconnect. In this paper, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for today's integrated circuits are discussed. A model that includes some of the most prevalent characteristics is designed and tested using the most current benchmark circuits released by IBM. In addition, one application of the length estimation is proposed in which a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented. This model shows that the corrector step can improve the final placement results by up to 33% for special cases.     

Improved diagnosis using enhanced fault dominance

Defect diagnosis can benefit from fault dominance relations to reduce the set of defect candidate sites. This paper presents new fault dominance collapsing operators that further reduce the set of candidates considered during the initial phase of diagnosis. In contrast to existing dominance-based methods which operate on pairs of faults, the proposed method operates on sets of faults. Fault-related entities are generated to guide the diagnosis process. The proposed collapsing operators can be used to accelerate effect-cause diagnosis. Experimental results demonstrate that the proposed method achieves a higher collapsing ratio than existing methods.