A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-amps

A simple dynamic biasing scheme to extend the input/output range of cascode amplifiers is introduced. It requires minimum extra hardware and no additional power consumption. A dynamic biased telescopic op-amp is discussed as an application example. Experimental results of a fabricated test chip in 0.5 μm CMOS technology are presented that verify the proposed technique.     

A new IMM algorithm using fixed coefficients filters (fastIMM)

In this paper we present an new approach based on two filters αβ$\alpha \beta$ and αβγ$\alpha \beta \gamma$ using Interacting Multiples Models (IMM) design instead of a Kalman filter second and third order for the tracking a single maneuver target. The comparison between the proposed filter and the IMM improves the computing time amount about 60% while having a high accuracy.     

An improved quantum-inspired evolutionary algorithm for coding resource optimization based network coding multicast scheme

This paper investigates how to minimize the required coding resources in network-coding-based multicast scenarios. An evolutionary algorithm (MEQEA) is proposed to address the above problem. Based on quantum-inspired evolutionary algorithm (QEA), MEQEA introduces multi-granularity evolution mechanism which allows different chromosomes, at each generation, to have different rotation angle step values for update. In virtue of this mechanism, MEQEA significantly improves its capability of exploration and exploitation, since its optimization performance is no longer overly dependant upon the single rotation angle step scheme shared by all chromosomes. MEQEA also presents an adaptive quantum mutation operation which is able to prevent local search efficiently. Simulations are carried out over a number of network topologies. The results show that MEQEA outperforms other heuristic algorithms and is characterized by high success ratio, fast convergence, and excellent global-search capability.     

Sharp-rejection microstrip bandpass filters with multiple transmission zeros

A simple design of a sharp-rejection microstrip bandpass (BPF) filter is presented. By creating multiple transmission zeros in the lower and upper stopbands, sharp rejection characteristics are obtained. The basic filter unit consists of a single parallel coupled-line section and an open-ended stub. A lossless transmission line model approach is used to derive the design equations for frequency responses and transmission zero positions. The bandwidths are controllable by the zero locations that in turn are controlled by varying the impedances of the configuration. To validate theoretical predictions, two prototype BPFs operating at lower band 2.4 GHz of WLAN are fabricated in microstrip form.     

Electronically tunable high-input impedance voltage-mode universal biquadratic filter based on simple CMOS OTAs

This paper describes a new electronically tunable three inputs and single output voltage-mode universal biquadratic filter based on simple CMOS operational transconductance amplifiers (OTAs) and grounded capacitors. The proposed configuration provides lowpass, highpass, bandpass, bandstop and allpass voltage responses at a high impedance input terminal, which enable easy cascadability. Additionally, the circuit parameters ω_o${\omega }_o$ and Q   can be set orthogonally by adjusting the transconductances and grounded capacitors. The filter also offers an independent electronic control of parameters ω_o${\omega }_o$ by adjusting the transconductance through the bias current/voltage of the OTA. For realizing all the filter responses, no critical component matching condition is required, and all the incremental parameter sensitivities are low. PSPICE simulation results are performed to confirm the theoretical analysis.     

Fully redundant decimal addition and subtraction using stored-unibit encoding

Decimal computer arithmetic is experiencing a revived popularity, and there is quest for high-performance decimal hardware units. Successful experiences on binary computer arithmetic may find grounds in decimal arithmetic. For example, the traditional fully redundant (i.e., the result and both of the operands are represented in a redundant format) and semi-redundant (i.e., the result and only one of the operands are redundant) binary addition schemes have influenced the design and implementation of similar decimal arithmetic units. However, special comparison and correction steps are required when decimal arithmetic algorithms are implemented on binary hardware. To circumvent these difficulties, alternative encodings of decimal digits and a variety of decimal arithmetic algorithms have been examined by many researchers over decades. In this paper we offer a new redundant decimal digit set [−8, 9] and a fully redundant addition/subtraction scheme. The proposed digit set, faithfully encoded as a mix of posibits, negabits, and unibits, is shown to obviate the need for any compare-to-9 operations and leads to minimal penalty subtraction using the addition circuitry. Moreover, conversion from the standard BCD encoding to the proposed stored-unibit encoding is possible with the latency of one logic level. However, the reverse conversion, like any other redundant to nonredundant conversion, involves carry propagation.     

Reducing leakage power with BTB access prediction

This paper investigates three architectural methods to reduce the leakage power dissipated by the BTB data array. The first method (called here window) periodically places the entire BTB data array into drowsy mode. A drowsy entry is woken up by the first access in the time interval and remains active for the remainder of the interval (window). There is an associated performance loss which is related to the size of the window, since there is a delay when a specific line must be woken up. The second method, awake line buffer (ALB), limits the number of active BTB entries to a predetermined maximum. While this reduces power dissipation it comes with a performance penalty that is relative to the size of the buffer. ALB, however, reduces the power dissipation of the data array more than the window method. The third method, 2-level ALB (2L-ALB), uses a two level buffer with the identical number of combined entries as the previous method. This method exploits the fact that many branches operate numerous times in a fixed sequence. By predicting the next BTB access, 2L-ALB achieves further reduction in leakage power without incurring any further performance loss, compared to the ALB method.     

A low-overhead and reliable switch architecture for Network-on-Chips

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation of the erroneous flits in NoC is prevented without any need to credit signals and, retransmission buffers. Using an HDL-based NoC simulator, the LRS is compared to two other widely used reliability enhancement methods: the Switch-to-Switch (S2S) and the End-to-End (E2E) methods. The simulation results show that the LRS consumes less power and provides higher performance compared to those of the E2E and S2S methods. More importantly, unlike the E2E and the S2S methods, the LRS has constant overheads, which makes it applicable in all working conditions. To validate the comparison, an analytical performance and reliability model is developed for the LRS, S2S and E2E methods. The results of the model match those obtained from the simulations while the proposed model is significantly faster.