Statistical analysis of large on-chip power grid networks by variational reduction scheme

One of the most critical challenges in today's CMOS VLSI design is the lack of predictability in chip performance at design stage. One of the process variabilities comes from the voltage drop variations in on-chip power distribution networks. In this paper, we present a novel analysis approach for computing voltage drops of large power grid networks under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called variational extended truncated balanced realization (varETBR), is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. After the reduction, Monte Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. varETBR calculates variational response Grammians by Monte Carlo based numerical integration considering both system and input source variations in generating the projection subspace. varETBR is very scalable for the number of variables and flexible for different variational distributions and ranges as demonstrated in experimental results. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 1900X faster than the Monte Carlo method and is much more scalable than one of the recently proposed approaches.     

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.     

Robust supergain beamforming for circular array via second-order cone programming

The phenomenon of supergain for a circular array and its robust beamforming are presented. The coplanar superdirective array gain of the circular array, although it is not so extreme as an endfire line array, outperforms a lot over that of a conventional delay-and-sum beamformer in isotropic noise fields when the inter-element spacings are much smaller than one-half wavelength. However, optimum beamforming algorithms can be extremely sensitive to slight errors in array characteristics. The performance are known to degrade significantly if some of underlying assumptions on the sensor array is violated. Therefore, white noise gain constraint is used to improve the robustness of the supergain beamformer against random errors. We show that the design of the weight vector of robust supergain beamformer can be reformulated as a form of second-order cone programming and resolved efficiently via the well-established interior point method. Results of computer simulation for a 24-element circular array confirm satisfactory performance of the approach proposed in this paper.     

High performance set associative translation lookaside buffers for low power microprocessors

A fast low power four-way set-associative translation lookaside buffer (TLB) is proposed. The proposed TLB allows single clock phase accesses at clock frequencies above 1 GHz. Comparisons to a conventional fully associative CAM tagged TLB, which is the type most commonly used in embedded processors, with the same number of entries on a 65 nm low standby power process show that the proposed design has 28% lower delay and up to 50% lower energy delay product. Unlike previous set-associative TLBs, which replicate the TLB to support multiple page sizes, multiple page sizes are supported on a way-by-way basis. Alternative conventional CAM tagged and set-associative TLBs are investigated with regard to access latency, power dissipation and hit rates.