Wavelength-tunable 40-GHz picosecond harmonically mode-locked fiber laser source

We demonstrate a novel 40-GHz mode-locked fiber laser that utilizes a single active device to provide both gain and mode-locking. The laser produces pulses as short as 2.2 ps, is tunable over a 27-nm band centered at 1553 nm, and exhibits long-term stability without cavity-length feedback control. The pulse train at 1556 nm was used in a 40-Gb/s transmission experiment over 45 km with a low 0.4-dB power penalty.     

Multilayer power printed structures suitable for controlling EMI noises generated in power converters

Electromagnetic interference (EMI) noises generated in power converters are diffused on the surface of conductors. This means influences occur from radiated EMI noises emitted from power transmission lines as well as conducted EMI noises transmitted from them. EMI noises diffusing on the surface of conductors are generally difficult to control using conventional concentrated constant theory. Thus, a new approach based on distributed constant circuit theory is needed in order to control EMI noises. A power converter structure to control EMI noises using multilayer power printed circuit technology is studied in this paper. A structure which can control EMI noises should simultaneously satisfy two conditions, i.e., one to shut down and one to attenuate EMI noises. The structure satisfying these conditions is studied through simulations using the Transmission-Line Modeling Method. The simulations show that the diffusion of EMI noises is controlled by dividing the flow of currents produced by EMI noises into the horizontal and perpendicular directions. That is, the horizontal current flow is controlled inside using the differences in the resistance produced from differences between inner and outer diameter of power transmission lines and the perpendicular current flow can be controlled by properly designing the thickness of the dielectric layer sandwiched between P-and N-power transmission lines with the symmetrical structure. Moreover, it is confirmed by simulations and experiments that the attenuation of EMI noises is affected by the width of the power transmission lines. It is expected that the results obtained in this paper can provide important rules when designing power converters with EMI noise control functions which use the multilayer power printed circuit technology.     

Contention-conscious transaction ordering in multiprocessor DSP systems

This paper explores the problem of efficiently ordering interprocessor communication (IPC) operations in statically scheduled multiprocessors for iterative dataflow graphs. In most digital signal processing (DSP) applications, the throughput of the system is significantly affected by communication costs. By explicitly modeling these costs within an effective graph-theoretic analysis framework, we show that ordered transaction schedules can significantly outperform self-timed schedules even when synchronization costs are low. However, we also show that when communication latencies are nonnegligible, finding an optimal transaction order given a static schedule is an NP-complete problem, and that this intractability holds both under iterative and noniterative execution. We develop new heuristics for finding efficient transaction orders, and perform an extensive experimental comparison to gauge the performance of these heuristics.     

Super-orthogonal space-time trellis codes

We introduce a new class of space-time codes called super-orthogonal space-time trellis codes. These codes combine set partitioning and a super set of orthogonal space-time block codes in a systematic way to provide full diversity and improved coding gain over earlier space-time trellis code constructions. We also study the optimality of our set partitioning and provide coding gain analysis. Codes operating at different rates, up to the highest theoretically possible rate, for different number of states can be designed by using our optimal set partitioning. Super-orthogonal space-time trellis codes can provide a tradeoff between rate and coding gain. Simulation results show more than 2-dB improvements over the codes presented in the literature while providing a systematic design methodology.     

Hot carrier analysis in low-temperature poly-Si thin-film transistors using pico-second time-resolved emission microscope

We have analyzed degradation of N-channel thin-film-transistor (TFT) under dynamic stress using a pico-second time-resolved emission microscope. We have successfully detected emission at pulse fall edge for the first time. Emission intensity increased with the decrease of pulse fall time. As the degradation depended on the pulse fall time, this dependence clearly illustrates that hot electrons are the dominant cause of the degradation under dynamic stress. Based on these dependences, we proposed a model considering electron traps in the poly-Si.     

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented     

A study of the energy consumption characteristics of cryptographic algorithms and security protocols

Security is becoming an everyday concern for a wide range of electronic systems that manipulate, communicate, and store sensitive data. An important and emerging category of such electronic systems are battery-powered mobile appliances, such as personal digital assistants (PDAs) and cell phones, which are severely constrained in the resources they possess, namely, processor, battery, and memory. This work focuses on one important constraint of such devices-battery life-and examines how it is impacted by the use of various security mechanisms. In this paper, we first present a comprehensive analysis of the energy requirements of a wide range of cryptographic algorithms that form the building blocks of security mechanisms such as security protocols. We then study the energy consumption requirements of the most popular transport-layer security protocol: Secure Sockets Layer (SSL). We investigate the impact of various parameters at the protocol level (such as cipher suites, authentication mechanisms, and transaction sizes, etc.) and the cryptographic algorithm level (cipher modes, strength) on the overall energy consumption for secure data transactions. To our knowledge, this is the first comprehensive analysis of the energy requirements of SSL. For our studies, we have developed a measurement-based experimental testbed that consists of an iPAQ PDA connected to a wireless local area network (LAN) and running Linux, a PC-based data acquisition system for real-time current measurement, the OpenSSL implementation of the SSL protocol, and parameterizable SSL client and server test programs. Based on our results, we also discuss various opportunities for realizing energy-efficient implementations of security protocols. We believe such investigations to be an important first step toward addressing the challenges of energy-efficient security for battery-constrained systems.     

Electrical and photoelectric properties of electrochemically fabricated SnO2/Cd0.4Zn0.6S/CdTe solar cells

Solar cells based on SnO₂/Cd_0.4Zn_0.6S/CdTe heterostructures are fabricated by electrochemical deposition, and the dependences of their electrical and photoelectric properties on the thermal annealing conditions are studied. It is shown that thermal annealing reduces the tunnel currents by almost two orders of magnitude. The best conditions of thermal annealing are determined (t = 300°C and τ = 9 min). These conditions provide the highest photosensitivity of the heterostructures under study (I _sc ≈ 21.2 mA/cm², U _oc ≈ 813 mV, and η = 14.7%).     

Waveguide probe structures for a multilayer magnetodielectric: An inverse problem

Direct and inverse problems are considered for diffraction by an open end of a rectangular waveguide (RW) with a flange that adjoins a piecewise inhomogeneous planar layered lossy medium. Also considered are similar diffraction problems for a junction of an RW and a rectangular resonator filled with a multilayer medium and a junction of two RWs, one of which contains a multilayer plate. Such open and shielded waveguide probe structures (WPSs) are used for determination and nondestructive testing of parameters of multilayer samples. The direct problem is formulated on the basis of admittance and impedance algorithms with consideration for losses existing in the medium, flange, and screens. In this case, the approximation of the given aperture field allows obtainment of explicit solutions for open and shielded WPSs in the form of integrals. Solution of the inverse problem that lies in determining thicknesses, permittivities, and permeabilities of the layers from measured values of the magnitude of the reflection coefficient is obtained by minimizing the corresponding least-squares error and by constructing artificial neural networks. In order to increase the accuracy, it is proposed to use a two-port of errors and perform measurements for several positions of the sample with respect to the flange and different impedance conditions behind the sample.