A BiCMOS dynamic carry lookahead adder circuit for VLSIimplementation of high-speed arithmetic unit

A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 μm BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder     

Electrical coupling and impulse propagation in anatomically modeledventricular tissue

Computer simulations were used to study the role of resistive couplings on flat-wave action potential propagation through a thin sheet of ventricular tissue. Unlike simulations using continuous or periodic structures, this unique electrical model includes random size cells with random spaced longitudinal and lateral connections to simulate the physiologic structure of the tissue. The resolution of the electrical model is ten microns, thus providing a simulated view at the subcellular level. Flat-wave longitudinal propagation was evaluated with an electrical circuit of over 140,000 circuit elements, modeling a 0.25 mm by 5.0 mm sheet of tissue. An electrical circuit of over 84,000 circuit elements, modeling a 0.5 mm by 1.5 mm sheet was used to study flat-wave transverse propagation. Under normal cellular coupling conditions, at the macrostructure level, electrical conduction through the simulated sheets appeared continuous and directional differences in conduction velocity, action potential amplitude and V˙_max were observed. However, at the subcellular level (10 μm) unequal action potential delays were measured at the longitudinal and lateral gap junctions and irregular wave-shapes were observed in the propagating signal. Furthermore, when the modeled tissue was homogeneously uncoupled at the gap junctions conduction velocities decreased as the action potential delay between modeled cells increased. The variability in the measured action potential was most significant in areas with fewer lateral gap junctions, i.e., lateral gap junctions between fibers were separated by a distance of 100 μm or more     

Successive interference cancellation for multiuser asynchronousDS/CDMA detectors in multipath fading links

There has been an increasing interest in the use of code-division multiple access (CDMA) in cellular mobile and wireless personal communications. The choice of such multiaccess technique is attractive because of its potential capacity increases and other technical factors such as privacy and multipath rejection capabilities. However, it is well known that the performance of CDMA can be significantly degraded due to cochannel interference (CI) and the near-far effects. We consider the performance of direct-sequence (DS)-based CDMA over fading channels that are modeled as slowly varying Rayleigh-fading discrete multipath channels. Specifically, we propose and analyze an adaptive multistage interference cancellation strategy for the demodulation of asynchronous DS spread-spectrum multiple-access signals. Numerical results show that the proposed multistage detector, which alleviates the detrimental effects of the near-far problem, can significantly improve the system performance     

1.04 GBd low EMI digital video interface system using small swingserial link technique

In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd     

Modeling statistical dopant fluctuations in MOS transistors

The impact of statistical dopant fluctuations on the threshold voltage V_T and device performance of silicon MOSFET's is investigated by means of analytical and numerical modeling. A new analytical model describing dopant fluctuations in the active device area enables the derivation of the standard deviation, σV_T , of the threshold voltage distribution for arbitrary channel doping profiles. Using the MINIMOS device simulator to extend the analytical approach, it is found that σV_T, can be properly derived from two-dimensional (2-D) or three-dimensional (3-D) simulations using a relatively coarse simulation grid. Evaluating the threshold voltage shift arising from dopant fluctuations, on the other hand, calls for full 3-D simulations with a numerical grid that is sufficiently refined to represent the discrete nature of the dopant distribution. The average V_T-shift is found to be positive for long, narrow devices, and negative for short, wide devices. The fast 2-D MINIMOS modeling of dopant fluctuations enables an extensive statistical analysis of the intrinsic spreading in a large set of compact model parameters for state-of-the-art CMOS technology. It is predicted that V_T-variations due to dopant fluctuations become unacceptably large in CMOS generations of 0.18 μm and beyond when the present scaling scenarios are pursued. Parameter variations can be drastically reduced by using alternative device designs with ground-plane channel profiles     

On asymptotic approximation of a solution of a boundary-value problem for a nonlinear nonautonomous equation

On the basis of periodic Ateb functions, in the resonance and nonresonance cases, we construct the asymptotic approximation of one-frequency solutions of a boundary-value problem for a nonlinear nonautonomous equation.     

An efficient method of FIR filtering based on impulse responserounding

A new method of implementing efficient FIR filters is presented. It involves approximation of an equiripple FIR by a rounding operation and application of the derived impulse response by a simple recursive equation. The technique is extremely efficient for lowpass, highpass, bandpass, and bandstop filters with sharp transitions and low edge frequencies     

Simplified 0.35-μm flash EEPROM process using high-temperatureoxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheraltransistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O₂ anneal at 850°C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs     

Performance of the PAC optical packet network

For multiuser packet communications with unpredictable user demands (e.g., in a local or metropolitan area network), coordination and control of access to the frequency-division multiplexing (FDM) channels are difficult. B. Glance (J. Lightwave Technol., vol.10, pp.1323-1328, Sep 1992) proposed using a simple protection-against-collision (PAC) circuit to solve this media access problem and achieve full optical connectivity. The PAC system has the potential to interconnect hundreds of ports, each transmitting at several gigabits per second. Performance aspects of the PAC optical packet network are discussed here. The delay-throughout performance of this network is analyzed for uniform traffic patterns. The results show that in geographically distributed applications the maximum achievable throughput (normalized to the transmission rate) is typically between 0.4 and 0.5 per channel. In a centralized switch the (normalized) maximum achievable throughput can approach 0.8 per channel     

Spatial retardation of carrier heating in scaled 0.1-μmn-MOSFET's using Monte Carlo simulations

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V_d considerably less than the Si/SiO₂ injection barrier height φ_b. Simulation of both devices reveal that 1) although qV_d<φ_b, carriers can obtain energies greater than φ_b, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates