An Improved Architecture of Sixth Subharmonic Mixers in E-Band

An improved architecture of sixth subharmonic mixers is proposed in this paper. In order to meet the need of low conversion loss, antiparallel diodes are selected and the length of four open/shorted microstrip stubs at both sides of the antiparallel diodes are carefully designed. For any important idle frequency components which can’t be reused by the four stubs, reactive terminations are presented by adjusting the length of main RF and LO microstrip. The tested results indicate the lowest conversion loss is 26.1 dB at the radio frequency of 72 GHz, with fixed LO at 12 GHz. The proposed circuit architecture is suitable for the implementation of subharmonic mixers in E-band as well as other millimeter and submillimeter-wave regions where high quality and high frequency LOs are difficult to realize.     

A Novel Circuit Architecture for High Performance of High-order Subharmonic Mixers

A novel circuit architecture for high performance of high-order subharmonic (SH) mixers is proposed in this paper. According to the specified harmonic mixing order, one or more mixer diodes sub-arrays and corresponding power divider as well as phase shift network for RF and LO signals are arranged in the circuit. This proposed SH mixer circuit has improved conversion loss, wide dynamic range and high port isolation for high-order SH mixers. By phase cancellation of idle frequencies, the proposed SH mixer circuit can eliminate complicated design procedure of idle frequency circuits; by phase cancellation of leakage LO power to RF and IF port, and leakage RF power to LO port, the mixer circuit can get high port isolation in LO-IF/RF and RF-LO. The increased antiparallel diode pairs in each sub-array will also lead to well performance by lowering effective series resistance. The proposed SH mixer circuit can be easily realized with power divider and phase shift network for RF and LO signals.     

Address Generation Optimization for Embedded High-Performance Processors: A Survey

Nowadays embedded systems are growing at an impressive rate and provide more and more sophisticated applications characterized by having a complex array index manipulation and a large number of data accesses. Those applications require high performance specific computation that general purpose processors can not deliver at a reasonable energy consumption. Very long instruction word architectures seem a good solution providing enough computational performance at low power with the required programmability to speed up the time to market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more sophisticated architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the address generator unit, which comes in many flavors. Future architectures will have to deal with enormous memory bandwidth in distributed memories and the development of address generators units will be crucial for effective next generation of embedded processors where global trade-offs between reaction-time, bandwidth, energy and area must be achieved. This paper provides a survey of methods and techniques that optimize the address generation process for embedded systems, explaining current research trends and needs for future.

A Guard Code Scheme for Handover Traffic Management in WCDMA Systems

A key performance indicator of mobile wireless networks is failure probability of handover calls. In this paper, we propose a Call Admission Control policy which prioritizes handover calls over new calls in WCDMA systems. The OVSF code occupancy of the system is modeled by a Markov chain and the differentiation between handover and new calls is performed at the code level by introducing a “guard code” scheme. The scheme belongs to the well-known family of guard channel schemes and reserves some code capacity to favor the continuation of handover calls over the new calls. As the management of the general case is intractable, we solve certain numerical instances of the problem and manage to calculate several performance metrics like new call blocking and handover failure probabilities and code utilization. We complete our study with simulation results in the case of higher OVSF code tree capacity.

Performance analysis of an improved soft preemptive scheme for unevenly distributed traffic in optical wavelength-division multiplexing networks

In optical wavelength-division multiplexing (WDM) networks, traffic can be unevenly distributed across the network causing inefficient utilization of resources. To solve this problem, an improved soft preemptive (SP) scheme is proposed by considering dynamic resource distribution to deal with the uneven network utilization. A novel unevenly distributed traffic model in cross-time-zone networks is also presented to evaluate the efficiency of the new scheme. Compared with other schemes such as normal shortest path first (SPF) routing and wavelength conversion (WC), the new proposed scheme results demonstrate significantly better performance with respect to the network utilization and overall network blocking probability.

Improved Turbo Decoding Using Soft Combining Principle

One great challenge in wireless communication systems is to ensure reliable communications. Turbo codes are known by their interesting capabilities to deal with transmission errors. In this paper, we present a novel turbo decoding scheme based on soft combining principle. Our method improves decoding performance using soft combining technique inside the turbo decoder. Working on Max-Log-Maximum a Posteriori (Max-Log-MAP) turbo decoding algorithm and using an Additive White Gaussian Noise (AWGN) channel model and 16 Quadrature Amplitude Modulation (16QAM), simulation results show that the suggested solution is efficient and outperforms the conventional Max-Log-MAP algorithm in terms of Bit Error Rate (BER). The performance analysis is carried out in terms of BER by varying parameters such as the Energy per bit to Noise power spectral density ratio ( \(\text {E}_{\text {b}}/\text {N}_{\text {o}}\) ), and decoding iterations number. We call our proposed solution Soft Combined Turbo Codes.     

Special issue on microscopic image processing

The applications of biometric technology for automated personal identification become ubiquitous. Iris recognition is well known for high accuracy and reliability among the biometric traits. This paper presents an efficient noise-removing approach for non-cooperative iris recognition systems. Proposed method removed the noise factors including eyelids, eyelashes, reflections, out of framework, pupil and sclera. The novelty is to detect eyelashes and reflections through finding appropriate thresholds using a procedure called statistical decision making. The eyelids are detected using parabolic Hough transform in normalized iris image to increase computational speed. In addition, a coarse-to-fine strategy for accurate and fast iris localization is proposed. The Gabor-wavelet and a novel encoding strategy proposed in our previous work are also used here to generate the iris codes. We elaborate the principle of mask code generation to assign noisy bits in an iris code to exclude them in matching step. Experimental results on CASIA-IrisV3-Interval database show superiority of the proposed scheme among other state-of-the-art methods available in the literature.     

ADAPTIVE STEP－SIZE CONSTANT MODULUS ALGORITHM FOR BLIND MULTIUSER DETECTION IN DS－CDMA SYSTEMS

Blind Adaptive Step-size Constant Modulus Algorithm (AS-CMA) for multiuser detection in DS-CDMA systems is presented.It combines the CMA and the concept of variable step-size,uses a second LMS algorithm for the step size.It adjusts the step-size according to the minimum output-energy principle within a specified range,thus overcomes the problems of bad effect of fixed step-size LMS algorithm.Compared with Adaptive Step-size LMS (AS-LMS) algorithm,through simulations,this algorithm can adapt the changes of the environment,suppress multiple access interference in the dynamic environment and the stability of Signal to Interference Ratio (SIR) is superior to that of AS-LMS.     

Simulation of ship generated turbulent and vortical wake imaging by SAR

Synthetic Aperture Radar (SAR) imaging of ocean surface features is studied.The simulation of the turbulent and vortical features generated by a moving ship and SAR imaging of these wakes is carried out.The turbulent wake damping the ocean surface capillary waves may be partially responsible for the suppression of surface waves near the ship track.The vortex pair generating a change in the lateral flow field behind the ship may be partially responsible for an enhancement of the waves near the edges of the smooth area.These hydrodynamic phenomena as well as the changes of radar backscatter generated by turbulence and vortex are simulated.An SAR imaging model is then used on such ocean surface features to provide SAR images.Comparison of two ships‘simulated SAR images shows that the wake features are different for various ship parameters.