Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

The effects of nonlocal impact ionization on the speed of avalanche photodiodes

The nonlocal enhancement in the velocities of charge carriers to ionization is shown to outweigh the opposing effects of dead space, increasing the avalanche speed of short avalanche photodiodes (APDs) over the predictions of a conventional local model which ignores both of these effects. The trends in the measured gain-bandwidth product of two short InAlAs APDs reported in the literature support this result. Relatively large speed benefits are predicted to result from further small reductions in the lengths of short multiplication regions.     

High-performance self-aligned SiGeC HBT with selectively grown Si/sub 1-x-y/Ge/sub x/C/sub y/ base by UHV/CVD

Si/sub 1-x-y/Ge/sub x/C/sub y/ selective epitaxial growth (SEG) was performed by cold-wall, ultrahigh-vacuum chemical vapor deposition, and the effects of incorporating C on the crystallinity of Si/sub 1-x-y/Ge/sub x/C/sub y/ layers and the performance of a self-aligned SiGeC heterojunction bipolar transistor (HBT) were evaluated. A Si/sub 1-x-y/Ge/sub x/C/sub y/ layer with good crystallinity was obtained by optimizing the growth conditions. Device performance was significantly improved by incorporating C, as a result of applying Si/sub 1-x-y/Ge/sub x/C/sub y/ SEG to form the base of a self-aligned HBT. Fluctuations in device performance were suppressed by alleviating the lattice strain. Furthermore, since the B out diffusion could be suppressed by incorporating C, the cutoff frequency was able to be increased with almost the same base resistance. A maximum oscillation frequency of 174 GHz and an emitter coupled logic gate-delay time of 5.65 ps were obtained at a C content of 0.4%, which shows promise for future ultrahigh-speed communication systems.     

Analysis of feedback for higher order polarization-mode dispersion mitigation of NRZ 40-Gb/s optical transmission

First-order polarization-mode dispersion (PMD) compensation by means of a polarization controller and a differential delay line is not sufficient to guarantee error-free transmission for 40-Gb/s channels when higher order effects severely increase signal distortion. Higher order mitigation is possible by cascading more than one first-order block. However, only two-stage or three-stage devices remain simple enough to be actually controlled. The performance of such higher order PMD compensators is evaluated by means of numerical simulations. Two different feedback signals have been used, demonstrating that first-order and higher order PMD distortion of nonreturn-to-zero (NRZ) pulses at 40 Gb/s can be strongly mitigated for instantaneous values of the differential group delay (DGD) up to the bit slot, when the compensator is properly controlled.     

Construction and qualification of the pre-series MQM superconducting quadrupoles for the LHC insertions

The LHC insertions will be equipped with individually powered MQM superconducting quadrupoles, produced in three versions with magnetic lengths of 2.4 m, 3.4 m, and 4.8 m. The quadrupoles feature a 56 mm aperture coil, designed on the basis of an 8.8 mm wide Rutherford-type NbTi cable for a nominal gradient of 200 T/m at 1.9 K and 5390 A. A total of 96 quadrupoles are in production in Tesla Engineering, UK. In this report we describe the construction of the pre-series MQM quadrupoles and present the results of the qualification tests.     

Search for high-performance probe-fed stacked patches using optimization

High-performance circular probe-fed stacked patch antenna designs are explored through the use of numerical optimization. New trends are sought to aid understanding and to suggest novel solutions. We describe the optimization technique, present a new design trend relating efficiency and bandwidth to the choice of substrate dielectric, and propose and demonstrate a novel, optimized antenna achieving 33% bandwidth whilst maintaining greater than 80% surface wave efficiency.     

End-to-end congestion control schemes: utility functions, random losses and ECN marks

We present a framework for designing end-to-end congestion control schemes in a network where each user may have a different utility function and may experience noncongestion-related losses. We first show that there exists an additive-increase-multiplicative-decrease scheme using only end-to-end measurable losses such that a socially optimal solution can be reached. We incorporate round-trip delay in this model, and show that one can generalize observations regarding TCP-type congestion avoidance to more general window flow control schemes. We then consider explicit congestion notification (ECN) as an alternate mechanism (instead of losses) for signaling congestion and show that ECN marking levels can be designed to nearly eliminate losses in the network by choosing the marking level independently for each node in the network. While the ECN marking level at each node may depend on the number of flows through the node, the appropriate marking level can be estimated using only aggregate flow measurements, i.e., per-flow measurements are not required.     

Miniaturized coplanar waveguide stop band filters based on multiple tuned split ring resonators

A novel compact stop band filter consisting of a 50 /spl Omega/ coplanar waveguide (CPW) with split ring resonators (SRRs) etched in the back side of the substrate is presented. By aligning SRRs with the slots, a high inductive coupling between line and rings is achieved, with the result of a sharp and narrow rejection band in the vicinity of the resonant frequency of the rings. In order to widen the stop band of the filter, several ring pairs tuned at equally spaced frequencies within the desired gap are cascaded. The frequency response measured in the fabricated prototype device exhibits pronounced slopes at either side of the stop band and near 0 dBs insertion loss outside that band. Since SRR dimensions are much smaller than signal wavelength, the proposed filters are extremely compact and can be used to reject frequency parasitics in CPW structures by simply patterning properly tuned SRRs in the back side metal. Additional advantages are easy fabrication and compatibility with MMIC or PCB technology.     

Improved RNS FIR filter architectures

A new architecture for implementing finite-impulse response (FIR) filters using the residue number system (RNS) is detailed. The design is based on using a restricted modulus set, with moduli of the form 2/sup n/,2/sup n/-1, and 2/sup n/+1. This does not restrict the modulus set to the common 3 modulus set {2/sup n/-1,2/sup n/,2/sup n/+1}, but any number of pairwise relatively prime moduli of this form, for example, {5,7,17,31,32,33}. Based on a comparison with a 2's complement design, the new RNS design can offer a significant speed improvement. The gain is obtained by using a set of small moduli, selected so as to minimize critical path delay and area. An algorithmic approach is used to obtain full adder based architectures that are optimized for area and delay. The modulus set is optimum based on cost parameters for each modulus. This new architecture presents a practical approach to implementing a fast RNS FIR filter.