Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow

Model-order reduction (MOR) is a typical approach to speed up the post-layout verification simulation step in circuit design. This paper studies the benefits of using circuit partitioning in a complete MOR flow. First, an efficient reduction algorithm package comprising of partitioning, reduction, and realization parts is presented. The reduction flow is then discussed using theoretical analysis and simulations from an array of 65-nm technology node interconnect circuits. It is shown that the reduction efficiency and computational costs quickly worsen with increased circuit size when using a direct projection-based MOR approach. In contrast, by using partitioning, the MOR can retain the scalability of the reduction problem, being computationally lighter and more efficient even with larger circuits. In addition, using partitioning may improve the robustness of the MOR flow in cases with circuits with many ports or sensitive verification simulations.