Analog circuit design optimization through the particle swarm optimization technique

This paper details the Particle Swarm Optimization (PSO) technique for the optimal design of analog circuits. It is shown the practical suitability of PSO to solve both mono-objective and multiobjective discrete optimization problems. Two application examples are presented: maximizing the voltage gain of a low noise amplifier for the UMTS standard and computing the Pareto front of a bi-objective problem, maximizing the high current cut off frequency and minimizing the parasitic input resistance of a second generation current conveyor. The aptness of PSO to optimize difficult circuit problems, in terms of numbers of parameters and constraints, is shown.     

How Crucial is Cooperation in Mitigating World Climate? Analysis with World-MARKAL

In order to study the conditions for a World self-enforcing agreement on climate change, we model cooperative and non-cooperative World climate strategies with an integrated version of the 15-region techno-economic MARKAL model in which abatement costs and climate related damages are both included. We first explain why the use of a technology oriented model may add value to the analysis of global GHG strategies. Based on the empirical finding of linear cumulative climate damages, the computation of Nash equilibrium can be reduced to solving a series of 15 independent linear programs, one per region. Moreover, assuming interregional transfers to share the global surplus of cooperation, our work adopts the point of view of dynamic partial equilibrium computation coupled with cooperative game-theoretic principles. The results illustrate how the non-cooperative strategy is closer to the base case than to the cooperative strategy, and the amount of side-payments sufficient to guarantee the stability of the cooperative strategy are calculated with four different rules. The internal (in)stability of farsighted coalitions without transfers (non-cooperation) is also analyzed. The current project appears to be the first one of the sort using a large and detailed technology explicit model such as MARKAL.     

A novel heuristic for multi-objective optimization of analog circuit performances

We present a novel heuristic for optimizing analog circuit performances. It deals with generating the Pareto front using the topological properties of the feasible solution space. This heuristic allows us generating optimal values of circuit parameters in reduced computation time and memory consumption. Unlike basic metaheuristics, it does not need optimization background from the user in order to be easily adapted to different applications. It can thus be smoothly integrated into an automated design flow. This novel approach enables us to further improve (good) performances that were already reached using other optimizing techniques. Robustness of the algorithm was proved using specific difficult test problems.     

Probabilistic behaviour of optical bin-packing solutions

The bin-packing problem is studied from a probabilistic view point. It is shown that, when the sizes of the n elements to be packed are drawn independently from a probability distribution F, then the minimum number of bins necessary for the packing of these n elements is asymptotically (a.e.) proportional to n in three cases. In all three cases, the constant of proportionality to n is explicitly given. Furthermore, in two of the cases, a heuristic is described which is asymptotically almost surely closed to the optimal solution.     

Optimizing performances of switched current memory cells through a heuristic

Optimally designing switched current (SI) memory cells is a hard task. In addition, it is usually limited to the design of ideal cells. Thus, in this paper we deal with optimizing these cells and precisely real ones using a heuristic. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design this kind of cells. Also, besides maximizing performances and minimizing famous error sources, we focus on optimally sizing transistors forming switches and bias sources. The optimization procedure, developed with help of C++ software, allows automatic design of the cell. It is also highlighted in the followings.     

Design of low power single-stage bias current control technique- based DVGA for LTE receivers

Analog Integrated Circuits and Signal Processing - In this study, a novel single-stage Digital Variable Gain Amplifier architecture (DVGA) was presented for Long Time Evolution (LTE) receivers. The...