A new Pd-oxide-Al/sub 0.3/Ga/sub 0.7/As MOS hydrogen sensor

A new and interesting Pd-oxide-Al/sub 0.3/Ga/sub 0.7/As MOS hydrogen sensor has been fabricated and studied. The steady-state and transient responses with different hydrogen concentrations has been measured at various temperatures. Based on the large Schottky barrier height and presence of oxide layer, the studied device exhibits a high hydrogen detection sensitivity and wide temperature operating regime. The studied device exhibits the low-leakage current and obvious current changes when exposed to hydrogen-contained gas. Even at room temperature, a very high hydrogen detection sensitivity of 155.9 is obtained when a 9090 ppm H/sub 2//air gas is introduced. Furthermore, when exposed to hydrogen-contained gas at 95/spl deg/C, both the forward and reverse currents are substantially increased with increased hydrogen concentration. In other words, the studied device can be used as a hydrogen sensor under the applied bidirectional bias. Under the applied voltage of 0.35 V and 9090 ppm H/sub 2//air hydrogen ambient, a fast adsorption response time about 10 s is found. The transient and steady-state characteristics of hydrogen adsorption are also investigated.     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

The First Template‐Free Growth of Crystalline Silicon Microtubes

A simple template‐free high‐temperature evaporation method was developed for the growth of crystalline Si microtubes for the first time. As‐grown Si microtubes were characterized using X‐ray diffraction, scanning electron microscopy, transmission electron microscopy, and room‐temperature photoluminescence. The lengths of the Si tubes can reach several hundreds of micrometers; some of them have lengths on the order of millimeters. Each tube has a uniform outer diameter along its entire length, and the typical outer diameter is ≈ 2–3 μm. Most of the tubes have a wall thickness of ≈ 400–500 nm, though a considerable number of them exhibit a very thin wall thickness of ≈ 50 nm. Room‐temperature photoluminescence measurement shows the as‐synthesized Si microtubes have two strong emission peaks centered at ≈ 589 nm and ≈ 617 nm and a weak emission peak centered at ≈ 455 nm. A possible mechanism for the formation of these Si tubes is proposed. We believe that the present discovery of the crystalline Si microtubes will promote further experimental studies on their physical properties and smart applications.     

连续波雷达测距中的解模糊技术

研究连续波雷达测距中的距离模糊问题，分析几种常用解模糊方法的性能，并讨论参差比的选取对测距范围的影响。     

Derivation of a second-order switching surface in the boundary control of buck converters

A second-order switching surface in the boundary control of buck converters is derived in this letter. The formulated switching surface can make the overall converter exhibit better steady-state and transient behaviors than the one with a first-order switching surface. The switching surface is derived by estimating the state trajectory movement after a switching action, resulting in a high state trajectory velocity along the switching surface. This phenomenon accelerates the trajectory moving toward the target operating point. The proposed control scheme has been successfully applied to a 120-W buck converter. The large-signal performance and a comparison with the first-order switching surface have been studied.     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

On the physical and logical topology design of large-scale optical networks

We consider the problem of designing a network of optical cross-connects (OXCs) to provide end-to-end lightpath services to large numbers of label switched routers (LSRs). We present a set of heuristic algorithms to address the combined problem of physical topology design (i.e., determine the number of OXCs required and the fiber links among them) and logical topology design (i.e., determine the routing and wavelength assignment for the lightpaths among the LSRs). Unlike previous studies which were limited to small topologies with a handful of nodes and a few tens of lightpaths, we have applied our algorithms to networks with hundreds or thousands of LSRs and with a number of lightpaths that is an order of magnitude larger than the number of LSRs. In order to characterize the performance of our algorithms, we have developed lower bounds which can be computed efficiently. We present numerical results for up to 1000 LSRs and for a wide range of system parameters such as the number of wavelengths per fiber, the number of transceivers per LSR, and the number of ports per OXC. The results indicate that it is possible to build large-scale optical networks with rich connectivity in a cost-effective manner, using relatively few but properly dimensioned OXCs.     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.     

2-D symmetry: theory and filter design applications

In this comprehensive review article, we present the theory of symmetry in two-dimensional (2-D) filter functions and in 2-D Fourier transforms. It is shown that when a filter frequency response possesses symmetry, the realization problem becomes relatively simple. Further, when the frequency response has no symmetry, there is a technique to decompose that frequency response into components each of which has the desired symmetry. This again reduces the complexity of two-dimensional filter design. A number of filter design examples are illustrated.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.