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181.
182.
Yang Aiying Wang Ziyu Zhang Zhaoyi Chen Zhangyuan Wu Deming 《电子科学学刊(英文版)》2003,20(6):461-466
A 10Gbit/s recirculating system is configured with Chirped Fiber Bragg Grating (CFBG) for the dispersion compensation. For the first time, the transmission distance in the loop reaches 1000km with bit error rate of 10-9. The effect of the group delay ripple of the fiber grating is also investigated in the recirculating systems, and it is shown that the transmission distance is limited to 4 cycles (4×167.1km ) in the loop with the power penalty fluctuation below 1.0dB. Thus the group delay ripple should be reduced to allow for the wavelength drift of±5GHz. At the end of this letter, the principles are given for designing long haul recirculating systems with dispersion compensation CFBG. 相似文献
183.
High-performance and power-efficient CMOS comparators 总被引:1,自引:0,他引:1
Chung-Hsun Huang Jinn-Shyan Wang 《Solid-State Circuits, IEEE Journal of》2003,38(2):254-262
Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques. 相似文献
184.
Popular biorthogonal wavelet filters via a lifting scheme and its application in image compression 总被引:2,自引:0,他引:2
Cheng L. Liang D.L. Zhang Z.H. 《Vision, Image and Signal Processing, IEE Proceedings -》2003,150(4):227-232
A technique using a lifting scheme is presented for constructing compactly supported wavelets whose coefficients are composed of free variables locating in an interval. An efficient approach-based wavelet for image compression is developed by selecting the coefficients of the 9-7 wavelet filter and associated lifting scheme. Furthermore, the rationalised coefficients wavelet filter that can be implemented with simple integer arithmetic is achieved and its characteristic is close to the well known original irrational coefficients 9-7 wavelet filters developed by A. Cohen et al. (Commun. Pure Appl. Maths., vol.45, no.1, p.485-560, 1992). To reduce the computational cost of image coding applications further, an acceleration technique is proposed for the lifting steps. Software and hardware simulations show that the new method has very low complexity, and simultaneously preserves the high quality of the compressed image. 相似文献
185.
186.
讨论了一种用于∑-△A/D转换器的固定系数半带(half-band)FIR数字滤波器,分析了其线性相位特性和低通滤波特性,给出了频率仿真结果,以及在Cadence设计系统中的电路和版图实现。 相似文献
187.
Summary Carbon deposits on the surface ofRu/Fe2O3 catalysts used in the water-gas shift reaction have been investigated by Auger Electron Spectrometry. A correlation has been
found between the thickness of the carbon deposit and the catalytic activity in WGSR. The carbon deposit covers the metallic
active centers and blocks their contact with reagents. The dotting of the iron oxide support with sodium has been found to
reduce the amount of carbon deposit. . 相似文献
188.
文章介绍了一种新型的短波跳频通信技术——差分跳频,分析了差分跳频技术区别于常规跳频技术的主要特点。针对按序列检测的信号接收方法,对差分跳频通信系统在AWGN信道下的性能进行了理论分析,同时做出相应的计算机仿真,证实了差分跳频通信技术和按序列检测方法的结合,使通信系统在AWGN信道下的性能得到了比较显著的提升。 相似文献
189.
190.
Analysis and architecture design of variable block-size motion estimation for H.264/AVC 总被引:1,自引:0,他引:1
Ching-Yeh Chen Shao-Yi Chien Yu-Wen Huang Tung-Chien Chen Tu-Chih Wang Liang-Gee Chen 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(3):578-593
Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory. 相似文献