Effective Location Based Services with Dynamic Data Management in Mobile Environments

With the proliferation of mobile computing technologies, location based services have been identified as one of the most promising target application. We classify mobile information service domains based on feature characteristics of the information sources and different patterns of mobile information access. By carefully examining the service requirements, we identify the dynamic data management problem that must be addressed for effective location based services in mobile environments. We then devise a general architecture and cost model for servicing both location independent and location dependent data. Based on the architecture and cost model, we propose a set of dynamic data management strategies that employs judicious caching, proactive server pushing and neighborhood replication to reduce service cost and improve response time under changing user mobility and access patterns. Detail behavior analysis helps us in precisely capturing when and how to apply these strategies. Simulation results suggest that different strategies are effective for different types of data in response to different patterns of movement and information access. Shiow-yang Wu is an associate professor of the Department of Computer Science and Information Engineering at National Dong Hwa University, Hualien, Taiwan, R.O.C. He received the BS and MS degrees in computer engineering from National Chiao Tung University, Hsinchu, Taiwan, ROC, and the PhD degree in computer science from the University of Texas at Austin in 1984, 1986, and 1995, respectively. His research interests include data/knowledge bases, mobile computing, distributed processing, intelligence information systems, and electronic commerce. Kun-Ta Wu was born in Taipei, Taiwan, R.O.C., in 1976. He received the B.S. degree in computer science from Soochow University, Taipei, Taiwan, R.O.C., in 1999 and the M.S. degree in computer science and information engineering from National Dong Hwa University, Hualien, Taiwan, R.O.C., in 2001. Currently, he is an Assistant Researcher in the Domestic Division at Science and Technology Information Center, National Science Council, R.O.C., as a member of Information Gathering and Analysis Group of National Information and Communication Security Taskforce. His research interests include mobile computing, wireless network and information security.     

Cover Picture: Arresting,Fixing, and Separating Dimers Composed of Uniform Silica Colloidal Spheres (Adv. Funct. Mater. 12/2006)

In colloidal suspensions of silica, particles undergo constant collisions. By controlling various parameters, the repulsive barrier can be reduced, thereby substantially increasing the number of collision‐induced dimerization events. Xia and co‐workers report on p. 1627 that the dimers could be arrested and then permanently fixed by introducing a small amount of fresh tetraethylorthosilicate into the colloidal suspension, with monodisperse dimer yields of up to 50 %. This yield could be increased to 80 % by centrifugation in a density gradient medium. When fresh tetraethylorthosilicate is introduced into a colloidal suspension of silica spheres, it hydrolyzes and condenses in situ to arrest and fix the dimers resulting from constant collisions between the spheres. By optimizing the experimental parameters (including the length of aging time) and the diameter of the silica spheres, as well as the concentrations of counterions, water, and ammonia, it is possible to routinely produce monodisperse dimers with a yield as high as 50 %. When combined with centrifugation using a density gradient medium, the yield of such dimers could be further increased to 80 %. It is believed that this method will provide a simple and versatile approach to the high‐volume production of dimers from spherical colloids composed of different materials. These dimers may find widespread use in a range of applications such as fabrication of photonic crystals and fundamental studies related to colloidal science.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

Robust vector control of induction motors using full-order observer in consideration of core loss

This paper proposes a method for designing a robust full-order observer for vector-controlled induction motors taking core loss into account. Although conventional research focuses on parameter identification, global stability of the identification remains questionable. Therefore, robustness against some parameters is required. This paper describes the design of a robust full-order observer which takes core loss into account, using both the gain-scheduled H/sub /spl infin// control and the linear matrix inequality technique. This design always results in a stable controller. The robustness of the proposed method against variations of resistances is evaluated by experiments.     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.     

Experimental and numerical assessment of gate-lag phenomena in AlGaAs-GaAs heterostructure field-effect transistors (FETs)

Gate-lag effects are characterized in AlGaAs-GaAs heterostructure field-effect transistors (HFETs) by means of measurements and numerical device simulations. Gate lag increasingly affects device switching at increasing ungated recess extension, suggesting that responsible deep levels be located at the ungated, recess surface of the HFET. Gate lag diminishes by making the off-state gate-source voltage less negative and by increasing the drain bias. Increasing the temperature makes the turn-on transient faster at low drain bias, while slightly delaying it at high drain bias. Numerical device simulations accounting for acceptor-like traps at the ungated surface predict gate-lag phenomena in good agreement with experiments, reproducing correctly the observed bias and temperature dependences. Simulations show that surface states behave, during the turn-on transient, as hole traps capturing holes attracted at the ungated surface by the negative trapped charge.     

Lateral ion implant straggle and mask proximity effect

Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.     

Reducing CIC filter complexity

This paper provides several tricks to reduce the complexity and enhance the usefulness of cascaded integrator-comb (CIC) filters. The first trick shows a way to reduce the number of adders and delay elements in a multi-stage CIC interpolation filter. The result is a multiplierless scheme that performs high-order linear interpolation using CIC filters. The second trick shows a way to eliminate the integrators from CIC decimation filters. The benefit is the elimination of unpleasant data word growth problems.