A hybrid wafer-dicing process for GaAs MMIC production

A dicing process for GaAs MMIC (monolithic microwave integrated circuit) wafers using spin-on wax for wafer mounting and a hybrid process of wet chemical etching/mechanical sawing for chip dicing is described. This process minimizes ragged chip edges and reduces generation of microcracks in addition to the elimination of the plated gold burrs on the backside of the diced MMIC chips. This process gives a uniformity of -3 μm across a 2-in wafer following the completion of the whole backside process. This GaAs chip dicing technique is amenable to production because it exhibits both a very high chip yield (>90%) and nearly flawless edges     

Solution of a singular Cauchy problem of implicit form

Translated from Ukrainskii Matematicheskii Zhurnal, Vol. 43, No. 6, pp. 755–760, June, 1991.     

Breaking the Nyquist barrier

The author discusses the concept that data sampled beyond the Nyquist frequency is meaningless. A simple signal processing scheme to extend resolution to nearly twice the Nyquist without the problem of alias emerged. It starts by placing one-dimensional signals into a simulated sample-and-hold process in a Mathcad application     

A multilevel soliton communication system

A multilevel soliton communication system is proposed and assessed. In this system, at the transmitter end each channel transmits its data via fundamental solitons with a pre-specified amplitude (i.e., soliton width). At the receiver end we take advantage of the sensitive relationship between the amount or fundamental soliton self-wavelength shift and the width of the soliton in the subpicosecond region. We first compress the incoming soliton noises to the subpicosecond level and pass them through a short length of fiber at the end of which the pulses have become separated in the wavelength domain since each soliton, corresponding to a data channel, has experienced a different Raman self-wavelength shift. The channels are then easily separated by optical filters. We have derived the design constraint relations for such a system. We have then heuristically designed a 40 Gbs (four channels) system for a 1000 km propagation distance (total data-rate distance product of 40 Tb/km). Numerical simulations and noise analyses have verified the feasibility and practicality of the proposed system with very good design margins. The wavelength jitter is found to be much smaller than the desired filter spacing, and thus its contribution to the bit error rate is negligible. We also argue that the system is more tolerant to Gordon-Haus timing jitter than conventional TDM soliton systems. The system is all fiber and is, therefore very cost effective as it does not require sophisticated electro-optic and microwave circuits for demultiplexing. The system can potentially operate at much higher speeds than those achievable in conventional soliton systems and it can be used in parallel with WDM soliton system     

Pyrolysis of tertiarybutylphosphine at low pressure

The pyrolysis of tertiarybutylphosphine (TBP) has been studied in the low pressure conditions used for chemical beam epitaxy (CBE). The pyrolysis studies were carried out in low pressure reactors of two different configurations, one of which is a cracker cell designed for use in a CBE system. The reaction products were studied using a quadrupole mass spectrometer. The products observed are accounted for by a reaction mechanism involving homolysis of the parent TBP molecule to produce PH₂ and C₄H₉ radicals. These undergo subsequent reactions to form the stable products C₄H₈, PH₃ and H₂, with smaller amounts of P and P₂ being produced. The production of the sub-hydride PH₂ using this cracker cell design indicates that the use of partially cracked TBP may be a promising technique for reducing the amount of carbon incorporated into the growing epitaxial layer.     

Transistor equivalent circuits

This paper surveys the history of the electric-circuit representation of the transistor over the past fifty years. During the first two decades after the transistor was announced in 1948, primary emphasis was on small-signal equivalent circuits, which could be used for linear-circuit analysis and design. In addition, parameters of many of these equivalent circuits for the bipolar junction transistor, which are described, were related to the physical construction of the device. Approximately two-thirds of the paper is devoted to this period, when the writer personally contributed to this effort. By the beginning of the third decade, transistor circuits had became more complex, and circuit analysis was carried out with the help of digital computers. Interest then shifted away from small-signal equivalent circuits to “models” for computer-aided circuit design (CACD). This transition, including the models used in the widely used CACD program SPICE, is described. MOS transistors are treated only briefly; by the time MOS transistors became commercially viable devices, emphasis then also had shifted to “models” for CACD. In conclusion, the writer notes that there is still hope for us aficionados of small-signal equivalent circuits; new types of transistors are still being characterized in this manner