Implementation of a high speed frequency synthesizer employing a dual input phase accumulator

We present a new PLL based frequency synthesizer, in which we have replaced the conventional phase frequency detector and the dividers (programmable counters) with a sequential dual input phase accumulator (DIPA), consisting of a digital circuit employing adders, registers and a ladder. The main feature of the DIPA is that the two input frequencies are not required to be normalized (divided down) to the step frequency of the synthesizer. Instead, the two different high frequencies, that is the reference and the output frequency of the synthesizer, are applied directly. The DIPA samples and normalizes their phases at very high rates, calculates their phase difference, producing an output that consists of a dc component proportional to the phase difference and harmonics of the two input high frequencies. These harmonics are high frequencies and can easily be rejected by a wide bandwidth filter of the loop, without affecting the high convergence speed of the loop. Moreover, these harmonics do not generate spurs near the output frequency. The resolution of the DIPA based synthesizer depends only on the length of the digital word of the DIPA, and its convergence speed depends on the lower of the two input frequencies. The output of the DIPA is a linear function of the phase difference of the two input frequencies and its dynamic range exceeds the limit of ±2π that governs the conventional phase detectors. Thus, the proposed frequency synthesizer based on the DIPA has low phase noise, no spurs nearby the output frequency, high resolution and fast convergence rate. Additionally, the output frequency can be digitally modulated under the control of the closed loop, either by phase or frequency modulation.     

Analysis of an FRW cosmological model

The Einstein field equations for the Friedmann universe reduce to a system of three first-order equations for the space-like components and a constraint from the temporal component. We analyse the system from the viewpoints of symmetry and singularity analyses. The solutions of particular relevance to Cosmology are highlighted.      

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors

The continuous increase of the computational power of programmable processors has established them as an attractive design alternative, for implementation of the most computationally intensive applications, like video compression. To enforce this trend, designers implementing applications on programmable platforms have to be provided with reliable and in-depth data and instruction analysis that will allow for the early selection of the most appropriate application for a given set of specifications. To address this need, we introduce a new methodology for early and accurate estimation of the number of instructions required for the execution of an application, together with the number of data memory transfers on a programmable processor. The high-level estimation is achieved by a series of mathematical formulas; these describe not only the arithmetic operations of an application, but also its control and addressing operations, if it is executed on a programmable core. The comparative study, which is done using three popular processors (ARM, MIPS, and Pentium), shows the high efficiency and accuracy of the methodology proposed, in terms of the number of executed (micro-)instructions (i.e. performance) and the number of data memory transfers (i.e. memory power consumption). Using the proposed methodology we estimated an average deviation of 23% in our estimated figures compared with the measurements taken from the real execution on the CPUs. This work was supported by the project PENED ’99 ED501 funded by GSRT of the Greek Ministry of Development, and the project PRENED ’99 KE 874 funded by the Research Committee of the Democritus University of Thrace. This work was partially sponsored by a scholarship from the Public Benefit Foundation of Alexander S. Onassis (Minas Dasygenis). Nikolaos Kroupis was born in Trikala in 1976. He receiver the engineering degree and Ms.C. degree in Department of Electrical and Computer Engineering from Democritous University of Thrace, Greece, in 2000 and 2002, respectively. Since 2002 he has been a Ph.D. student at the Laboratory of Electrical and Electronic Materials Technology. His research interests are in software/hardware co-design of embedded system for signal processing applications. Nikos D. Zervas received a Diploma in Electrical & Computer Engineering from University of Patras, Greece in 1997. He received the Ph.D. degree in the Department of Electrical and Computer Engineering of the same University in 2004. His research interests are in the area of high-level, power optimization techniques and methodologies for multimedia and telecommunication applications. He has received an award from IEEE Computer Society in the context of Low-Power Design Contest of 2000 IEEE Computer Elements Mesa Workshop. Mr. Zervas is a member of the IEEE, ACM and of the Technical Chamber of Greece. Minas Dasygenis was born in Thessaloniki in 1976. He received his Diploma in Electrical and Computer Engineering in 1999, from the Democritus University of Thrace, Greece, and for his diploma Thesis he was honored by The Technical Chamber of Greece and Ericsson Hellas. In 2005, he received his PhD Degree from the Democritus University of Thrace. His research interests include low-power VLSI design of arithmetic circuits, residue number system, embedded architectures, DSPs, hardware/ software codesign and IT security. He has published more than 20 papers in international journals and conferences and he has been a principal researcher in three European research projects. Konstantinos Tatas received his degree in Electrical and Computer Engineering from the Democritus University of Thrace, Greece in 1999. He received his Ph.D. in the VLSI Design and Testing Center in the same University by June 2005. He has been employed as an RTL designer in INTRACOM SA, Greece between 2000 and 2003. His research interests include low-power VLSI design of DSP and multimedia systems, computer arithmetic, IP core design and design for reuse. Antonios Argyriou received the degree in Electrical and Computer engineering from the Democritous University of Thrace, Greece, in 2001, and the M.S. and Ph.D. degrees in Electrical and Computer engineering from the Georgia Institute of Technology, Atlanta, in 2003 and 2005, respectively. His primary research interests include wireless networks, mobile computing and multimedia communications. He is a member of the IEEE and ACM. Dimitrios Soudris received his Diploma in Electrical Engineering from the University of Patras, Greece, in 1987. He received the Ph.D. Degree in Electrical Engineering, from the University of Patras in 1992. He is currently working as Ass. Professor in Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Greece. His research interests include low power design, parallel architectures, embedded systems design, and VLSI signal processing. He has published more than 140 papers in international journals and conferences. He was leader and principal investigator in numerous research projects funded from the Greek Government and Industry as well as the European Commission (ESPRIT II-III-IV and 5th and 6th IST). He has served as General Chair and Program Chair for the International Workshop on Power and Timing Modelling, Optimisation, and Simulation (PATMOS). He received an award from INTEL and IBM for the project results of LPGD #25256 (ESPRIT IV). He is a member of the IEEE, the VLSI Systems and Applications Technical Committee of IEEE CAS and the ACM. Antonios Thanailakis was born in Greece on August 5, 1940. He received B.Sc. degrees in physics and electrical engineering from the University of Thessaloniki, Greece, 1964 and 1968, respectively, and the Msc. and Ph.D. Degrees in electrical engineering and electronics from UMIST, Manchester, U.K. in 1968 and 1971, respectively. He has been a Professor of Microelectronics in Dept. of Electrical and Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece, since 1977. He has been active in electronic device and VLSI system design research since 1968. His current research activities include microelectronic devices and VLSI systems design. He has published a great number of scientific and technical papers, as well as five textbooks. He was leader for carrying out research and development projects funded by Greece, EU, or other organizations on various topics of Microlectronics and VLSI Systems Design (e.g. NATO, ESPRIT, ACTS, STRIDE).     

Stereochemical variations on the colchicine motif. Peracid oxidation of thiocolchicone. Synthesis, conformation and inhibition of microtubule assembly

When 7-oxodesacetamidothiocolchicine (1) was treated with various peroxides in order to afford a Baeyer-Villiger rearrangement, a complex mixture of products was formed, which included the sulfoxide, (2) and sulfone, (3). When peracetic acid was used two additional products were formed; a C-ring lactone (4) and a ring-contracted allocolchicine derivative (5). The sulfoxide (2) was semi-preparatively resolved into enantiomers by chromatography on microcrystalline triacetylcellulose. Rotational barriers around the A-C pivot bond of, and were determined by dynamic 1H NMR analysis. The compounds, and exhibit moderate inhibition of tubulin polymerization, according to in vitro turbidity studies, whereas was inactive.     

Lattice collapse in mixed-valence samarium fulleride Sm(2.75)C(60) at high pressure

Sm(2.75)C(60) displays large negative thermal expansion behaviour in the temperature range 4.2-32 K at ambient pressure as a result of a quasi-continuous valence change from the larger Sm(2+) towards the smaller Sm(2.3+) ion. Here we use the powder synchrotron X-ray diffraction technique at ambient temperature and elevated pressures to study the compression behaviour in the pressure range 0-6 GPa. An abrupt hysteretic phase transition, accompanied by a dramatic volume decrease (approximately =6.0%) and a change in colour from black to golden was found at approximately =4 GPa induced by a sudden Sm valence transition from +2.3 towards +3. Such behaviour is typical of highly correlated Kondo insulators like SmS and makes Sm(2.75)C(60) the first known molecular-based member of this fascinating class of materials.     

Adaptive epileptic seizure prediction system

Current epileptic seizure "prediction" algorithms are generally based on the knowledge of seizure occurring time and analyze the electroencephalogram (EEG) recordings retrospectively. It is then obvious that, although these analyses provide evidence of brain activity changes prior to epileptic seizures, they cannot be applied to develop implantable devices for diagnostic and therapeutic purposes. In this paper, we describe an adaptive procedure to prospectively analyze continuous, long-term EEG recordings when only the occurring time of the first seizure is known. The algorithm is based on the convergence and divergence of short-term maximum Lyapunov exponents (STLmax) among critical electrode sites selected adaptively. A warning of an impending seizure is then issued. Global optimization techniques are applied for selecting the critical groups of electrode sites. The adaptive seizure prediction algorithm (ASPA) was tested in continuous 0.76 to 5.84 days intracranial EEG recordings from a group of five patients with refractory temporal lobe epilepsy. A fixed parameter setting applied to all cases predicted 82% of seizures with a false prediction rate of 0.16/h. Seizure warnings occurred an average of 71.7 min before ictal onset. Similar results were produced by dividing the available EEG recordings into half training and testing portions. Optimizing the parameters for individual patients improved sensitivity (84% overall) and reduced false prediction rate (0.12/h overall). These results indicate that ASPA can be applied to implantable devices for diagnostic and therapeutic purposes.     

The Design of an Allo-Optical Packet Switching Network

Recent advances in the all-optical signal processing domain report high-speed and nontrivial functionality directly implemented in the optical layer. These developments mean that the all- optical processing of packet headers has a future. In this article we address various important control plane issues that must be resolved when designing networks based on all-optical packet-switched nodes.     

Service configuration and user profiling in 4G terminals

This paper presents a middleware platform for managing devices that operate in heterogeneous environments. The proposed management framework supports terminal-controlled, preference-based access network selection. Two separate problems are identified in this domain: one involving the computation of optimal allocations of services to access networks and quality levels (service configuration), and one concerning the dynamic inference of the user’s preferences, according to the usage context (user profiling). This paper includes an approach to the definition, mathematical formulation and solution of both these problems. Indicative results of the proposed solution methods are presented in the context of a real-life scenario simulating a day in the life of an ordinary user.     

Coping with TiVo: Opportunities of the networked digital video recorder

Despite the progressive switch to digital TV, there has not been any significant change to the value chain of the TV industry. At the same time, the introduction of novel information and communication technologies, such as the digital video recorder (DVR) and efficient Peer-to-Peer (P2P) content distribution, have been regarded as a threat to the established broadcast business players. Previous research has described these threats and has suggested competitive strategies, but it has not investigated the opportunities. This work aims to identify a framework of new business models that take advantage of the networked DVR. For this purpose, we examined the TV literature from diverse academic disciplines, such as mass communication, computer engineering and advertising research. We have also collaborated with network and multimedia engineers, with broadcasters, and we examined novel interactive television (ITV) prototypes. The findings suggest that the networked DVR could be exploited to provide personalized channels and that the dynamic advertising insertion could be introduced as an effective advertising format. In the light of these findings, the TV industry should consider the pro-active adoption and facilitation of the networked DVR infrastructure.