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181.
This paper studies a particular single-stage power-factor-correction (PFC) switching regulator employing a discontinuous-conduction-mode (DCM) boost-input cell and a continuous-current-mode (CCM) forward output cell. Although this single-stage PFC regulator can provide a reasonably high power factor when its PFC stage is operating in discontinuous mode, substantial reduction in line-current harmonics is possible by applying a suitable frequency-modulation scheme. This paper derives a frequency-modulation scheme and proposes a practical implementation using a simple translinear analog circuit. A quantitative analysis on the total harmonic distortion (THD) of the line current when the circuit is subject to a limited range of frequency variations is presented along with some considerations for practical design. Experimental data obtained from a prototype confirms the effectiveness of the proposed frequency-modulation scheme. The proposed analog translinear circuit allows custom integrated circuit implementation, making it a viable low-cost solution to the elimination of line-current harmonics in switching regulators  相似文献   
182.
For pt.I see IEEE Trans. Neural Networks, vol.1, p.167-78 (1990). Parallel, self-organizing, hierarchical neural networks (PSHNNs) involve a number of stages with error detection at the end of each stage, i.e., rejection of error-causing vectors, which are then fed into the next stage after a nonlinear transformation. The stages operate in parallel during testing. Statistical properties and the mechanisms of vector rejection of the PSHNN are discussed in comparison to the maximum likelihood method and the backpropagation network. The PSHNN is highly fault tolerant and robust against errors in the weight values due to the adjustment of the error detection bounds to compensate errors in the weight values. These properties are exploited to develop architectures for programmable implementations in which the programmable parts are reduced to on-off or bipolar switching operations for bulk computations and attenuators for pointwise operations  相似文献   
183.
A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage Vd considerably less than the Si/SiO2 injection barrier height φb. Simulation of both devices reveal that 1) although qVdb, carriers can obtain energies greater than φb, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates  相似文献   
184.
Pattern classification is frequently performed using the k-nn algorithm or a neural network. The choice of parameters for the former is often difficult and the amount of data which has to be stored in the classifier can be high. Neural network classifiers can overcome some of these problems but learning is often unreliable and slow. An alternative which combines some of the best features of the k-nn and neural network classifier is described by the authors. The classifier is called a packed hyper-ellipsoid classifier  相似文献   
185.
"Photolithographic packaging (PL-pack) with selectively occupied repeated transfer (SORT)" is proposed for optoelectronic microsystem integration. PL-pack with SORT integrates different types of thin-film device pieces into one substrate with desired configurations using an all-photolithographic process. A process design example is presented for a scalable film optical link multichip-module (S-FOLM). A preliminary estimation reveals that PL-Pack with SORT will achieve III-V epitaxial material saving of <1/100 and module cost reduction of <1/10, compared with flip-chip-bonding-based packaging. The result indicates that the process will save on cost and resources simultaneously. A critical issue is how to simplify the procedure for distributing thin-film device pieces onto a substrate. SORT is found to reduce the distribution step count typically by factor of <1/10-1/10000 compared with the conventional one-by-one method. PL-pack with SORT will be extended to the 3R process (reduce, reuse, recycle), which is generally applied to a variety of device/module fabrications  相似文献   
186.
Double-crystal x-ray rocking curve (DCRC) and secondary-ion mass-spectroscopy (SIMS) measurements have been performed to investigate the effect of rapid thermal annealing on the interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd0.96Zn0.04Te (211)B substrates by molecular beam epitaxy. The sharp satellite peaks of the DCRC measurements on a 100-period HgTe/CdTe (100Å/100Å) superlattice show a periodic arrangement of the superlattice with high-quality interfaces. The negative direction of the entropy change obtained from the diffusion coefficients as a function of the reciprocal of the temperature after RTA indicates that the Hg diffusion for the annealed HgTe/CdTe superlattice is caused by an interstitial mechanism. The Cd and the Hg concentration profiles near the annealed HgTe/CdTe superlattice interfaces, as measured by SIMS, show a nonlinear behavior for Hg, originating from the interstitial diffusion mechanism of the Hg composition. These results indicate that a nonlinear interdiffusion behavior is dominant for HgTe/CdTe superlattices annealed at 190°C and that the rectangular shape of HgTe/CdTe superlattices may change to a parabolic shape because of the intermixing of Hg and Cd due to the thermal treatment.  相似文献   
187.
The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications  相似文献   
188.
The low temperature lifetime of electrons excited in the 2p?1 donor level of n-GaAs has been studied in a far-infrared pump-probe experiment. The measurement has been carried out using a pulsed far-infrared molecular gas laser working at a wavelength of 292µm, with the sample in a magnetic field of 5.1 T, resonant with the 1so?2p?1 transition. Two FIR pulses are sliced from one FIR-laser pulse by means of optical switching techniques using two Q-switched Nd:YAG lasers. The first pulse is used to saturate the transition, while the second pulse probes the return of the population in the excited state towards thermal equilibrium as a function of the time delay after the excitation pulse. The value of 350±50 ns found for the lifetime falls in line with CW saturation results on materials with other doping concentrations.  相似文献   
189.
A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10*14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450 000 transistors on 92 mm2  相似文献   
190.
Three-dimensional electromagnetic cross-well inversion   总被引:1,自引:0,他引:1  
An inversion algorithm for a vertical magnetic dipole source and a vertical magnetic field component receiver is presented. A three-dimensional integral equation algorithm is used for calculating the electromagnetic response of a particular trial reservoir model. The inversion formalism used is the Marquardt technique of nonlinear least-squares optimization. The system derivatives are calculated using an exact expression derived from reciprocity. The derivative calculation involves introducing sources at the receiver locations with subsequent back-substitution into the impedance matrix equation. The inversion algorithm was tested on data gathered with a laboratory scale model. Convergence to the neighborhood of the correct model from distant initial trial models is good  相似文献   
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