A 150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 μm BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55°C     

A video DSP with a macroblock-level-pipeline and a SIMD typevector-pipeline architecture for MPEG2 CODEC

A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 μm triple-layer-metal CMOS technology. This 17.00 mm×15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2's and a motion estimation (ME) unit, and one VDSP2 respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V     

Latest advances in camcorder technology

Camcorders have been developed to be compact with high performance. Latest advancement of key technologies and devices such as digital signal processing LSI, six-layer printed circuit board with micro chips, high-speed power lens with linear motor, 103 K pixels 0.7-in LCD electronic viewfinder, and high-energy Li-ion battery are described. High-band format is also explained     

Engineering a small system

“Do it right first time” is the slogan of systems engineering. The approach can benefit all types of development projects, from smaller commercial products to large government projects, because the objective is the same: to design a high-quality product as fast and efficiently as possible. The author describes how the key to this process is translating a customer's need into a set of specifications that drive the system's design     

Multiple cluster beamspace and resolution-enhanced ESPRIT

This paper addresses approaches to enhancement of the resolution of one or more clusters of closely spaced emitters. The TLS-ESPRIT algorithm is considered, as applied in beamspace and in element space, in conjunction with resolution enhancement. Beamspace (BS)-ESPRIT employs a matrix beamformer as a preprocessor to map the sensor space into a lower dimensional beamspace. Resolution enhanced (RE)ESPRIT employs a matrix beamformer as a left weighting of the signal subspace eigenvector matrix for enhancing the resolution of ESPRIT. This paper specifically discusses several types of these beamformer matrices, which differ in the way that they treat source clusters other than of interest. Our objective is to clearly define approaches and identify their relative merits, through discussion and illustrative simulation, so as to provide an understanding of how to proceed in designing an ESPRIT algorithm     

A noise resistant synchronization scheme for HDTV images

A method that increases the error resistance of the HDTV system and offers graceful picture degradation in the presence of bit errors, is presented. Due to the nature of the presently proposed compression schemes for HDTV systems, an error in a data bit does not only affect the block the bit belongs to, but unfortunately the effects of this error may perpetuate to the following blocks. This is because a bit error may cause loss of synchronization between the data bits and the picture blocks they represent. Our method restricts the effects of a bit error to a picture block whose size is significantly smaller than those used by the HDTV systems. We achieve synchronization by transmitting a header-word for each such synchronization block. Each header-word contains the number of data bits representing the compressed block. This header-word is protected by two levels of FEC code. To decrease the number of extra bits needed by the header-words, two different synchronization block sizes are used, a relatively small block size for the reference frames and a larger size for the inter-frames. The resulting method improves the quality of the picture in the presence of errors and defers the SNR at which the HDTV picture suddenly deteriorates by 2.5 to 3 dB. It also allows operation at higher order modulation transmission schemes, e.g., 32-QAM instead of 16-QAM, without the requirement of increased signal power     

A spectrally efficient constant envelope modulation technique forPCS and mobile communications

A newly developed constant envelope FQPSK modem/radio architecture, which employs a modified double-jump (DJ) filter in the cross-correlated FQPSK system, is proposed for personal communications systems (PCS) and mobile radio applications. Power efficiency, spectrum efficiency, BER, and system capacity of this system are investigated in a non-linear amplified (NLA) Rayleigh fading environment. We demonstrate that with the simplest threshold detectors (binary robust eye diagrams in I and Q channels), this system is 4-7 dB more power efficient than the US digital cellular and Japanese Handyphone standard π/4-QPSK, 50%-100% more spectrally efficient than the European standard GMSK, and it almost double the capacity of GMSK     

Random telegraph signal currents and low-frequency noise injunction field effect transistors

The detailed study of random telegraph signal (RTS) currents and low-frequency (LF) noise in semiconductor devices in recent years has confirmed their cause and effect relationship. In this paper we describe the physical mechanisms responsible for RTS currents in any device. The methods for calculating the amplitudes and characteristic times of the RTS currents produced by traps with known electrical characteristics and locations are described. The noise spectra in junction field effect transistors (JFET's) resulting from traps in the silicon or the oxide are derived as a function of basic device parameters, operating conditions and temperature. Experimental results verifying the predictions of the models are presented     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance     

In-plane transport properties of Si/Si1-xGexstructure and its FET performance by computer simulation

Transport properties of ungated Si/Si_1-xGe_x are studied by an ensemble Monte Carlo technique. The device performance is studied with a quantum hydrodynamic equation method using the Monte Carlo results. The phonon-scattering limited mobility is enhanced over bulk Si, and is found to reach 23000 cm²/Vs at 77 K and 4000 cm²/Vs at 300 K. The saturation velocity is increased slightly compared with the bulk value at both temperatures. A significant velocity overshoot, several times larger than the saturation velocity, is also found. In a typical modulation-doped field-effect-transistor, the calculated transconductance for a 0.18 μm gate device is found to be 300 mS/mm at 300 K. Velocity overshoot in the strained Si channel is observed, and is an important contribution to the transconductance. The inclusion of the quantum correction increases the total current by as much as 15%