RLS-based initialization for per-tone equalizers in DMT receivers

Per-tone equalization has recently been proposed as an alternative receiver structure for discrete multitone-based systems improving upon the well-known structure based on time-domain equalization. Fast initialization of all the equalizer coefficients has been identified as an open problem. In this letter, a recursive initialization scheme based on recursive least squares with inverse updating is presented for the per-tone equalizers. Simulation results show convergence with an acceptably small number of training symbols. Complexity calculations are made for per-tone equalization and for the case where tones are grouped. It is demonstrated with an example that in the latter case, initialization complexity becomes sufficiently low and comparable to complexity during data transmission.     

Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived and a reduced-complexity algorithm is developed for computation of the proposed computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for the computation of these transforms using the common-core algorithm. The proposed scheme not only leads to a systolic-like regular and modular hardware for computing these transforms, but also offers significant improvement in area-time efficiency over the existing structures. The structure proposed here is devoid of complicated input/output mapping and does not involve any complex control. Unlike the convolution-based structures, it does not restrict the transform length to be a prime or multiple of prime and can be utilized as a reusable core for cost-effective, memory-efficient, high-throughput implementation of either of these transforms     

An optically clocked transistor array with dual serial-to-parallel and parallel-to-serial conversion capability for optical label swapping

We propose an optically clocked transistor array optoelectronic integrated circuit (OEIC) for both serial-to-parallel and parallel-to-serial conversion (demux/mux), enabling an interface between high-speed asynchronous burst optical labels and CMOS circuitry for optical label swapping. Dual functionality of the OEIC reduces size, power, and cost of the optical label swapper. The capability for greater than 20-Gb/s conversion operation is demonstrated.     

Laterally coupled buried heterostructure high-Q ring resonators

All-buried InP-InGaAsP ring resonators laterally coupled to bus waveguides are demonstrated. The buried configurations offer a lower built-in refractive index step along the resonator periphery, which affords enhanced optical coupling coefficients between the waveguides and reduced scattering losses caused by the resonator sidewall imperfections. Very low optical intensity attenuations of 0.4 cm/sup -1/ and coupling-limited quality factors of greater than 10/sup 5/ are observed from 200-/spl mu/m-radii ring resonators. The measured spectral linewidth is as narrow as 0.0145 nm.     

A decision support system for interactive decision making - Part II: analysis and output interpretation

For pt.I see ibid., p.42-55 (2003). The development of a comprehensive decision support system, GMCR II, for the systematic study of real-world interactive decision problems is presented. The companion paper (Part I), discusses how GMCR II elicits, stores, and manages conflict models; here (Part II), the focus is on GMCR IIs analysis and output interpretation subsystems. Specifically, this paper describes the powerful and efficient analysis engine contained in GMCR II, its informative output presentation and interpretation facilities, and a number of follow-up analyses. Furthermore, an illustrative case study is used to demonstrate how GMCR II can be conveniently applied in practice.     

Consideration of Femtosecond Radiation Generation on NewSUBARU Storage Ring

We studied on realization of short pulse gamma ray and X-ray simultaneously induced by a femtosecond laser on NewSUBARU storage ring. Based on the fact that the transverse dimensions of electron beam are much shorter than the longitudinal one, the laser light is arranged to collide the electron beam at a right angle to generate femtosecond pulse gamma ray, furthermore, the modulated part of the electron bunch gives rise to short pulse X-ray by synchrotron radiation from a downstream bending magnet. The temporal characteristic of the radiation is analyzed in this paper, as well as the performances are estimated.     

The extended quadratic residue code is the only (48,24,12) self-dual doubly-even code

An extremal self-dual doubly-even binary (n,k,d) code has a minimum weight d=4/spl lfloor/n/24/spl rfloor/+4. Of such codes with length divisible by 24, the Golay code is the only (24,12,8) code, the extended quadratic residue code is the only known (48,24,12) code, and there is no known (72,36,16) code. One may partition the search for a (48,24,12) self-dual doubly-even code into three cases. A previous search assuming one of the cases found only the extended quadratic residue code. We examine the remaining two cases. Separate searches assuming each of the remaining cases found no codes and thus the extended quadratic residue code is the only doubly-even self-dual (48,24,12) code.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported