Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.     

A novel discrete control strategy for independent stabilization of parallel three-phase boost converters by combining space-vector modulation with variable-structure control

We propose a discrete nonlinear controller, developed in a synchronous frame, for a parallel three-phase boost converter consisting of two modules. The basic idea, however, can be extended to a system with N modules. Each of the closed-loop power-converter modules operates asynchronously without any communication with the other modules. The controller stabilizes the currents on the dq-axes and limits the flow of the pure-zero sequence current. It combines the space-vector modulation scheme with a variable-structure control, thereby keeping the switching frequency constant and achieving satisfactory dynamic performance.     

Influence of eccentricity on the frequency limitations of circular-pad via-holes

We study the influence of the technologically caused eccentricity of a circular-pad via-hole. We derive an eigenvalue equation using a rigorous method based on a linear transformation of the via-hole polar coordinates. The eigenvalue equation is used to compute the modal resonant frequencies and the modal fields of the eccentric via. It is shown that the via-hole misalignment shifts the modal frequencies and influences its frequency band. The proposed model is verified with published experimental data, and is also compared with results generated with the full-wave simulator Agilent Momentum-2002.     

Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs

A method to estimate the acquisition time for the clock and data recovery (CDR) IC using the linear phase-locked loop (PLL) technique is proposed. Estimations using the method follow the measured acquisition time for the PLL with any loop parameters, which makes it possible to design the CDR IC for various targets.     

Properties determining choice of mother wavelet

Properties of wavelets with finite as well as infinite support are summarised to facilitate mother wavelet selection in a chosen application. The quantitative guidelines reduce dependence on trial-and-error schemes resorted to for selection and underscore the importance of such selection in any application of interest. In wavelet-based image sequence superresolution, studied during the last four years, the use of a B-spline mother wavelet is justified.     

Monolithic integration of a 5.3 GHz regenerative frequency divider using a standard bipolar technology

A monolithic microwave frequency divider IC with an operating range of 1.4?5.3 GHz was developed and fabricated in a standard bipolar technology. The circuit operates on the principle of `regenerative frequency division?. Compared to the most popular divider concepts based on a master-slave D-flip-flop, an almost twice as high input frequency can be divided, provided that the same technology is used. A further advantage is the low power consumption.     

Simple approach to analysis of switched-capacitor circuits with nonideal op-amps

A possible method for the simulation of nonideal op-amps with a finite gain and bandwidth by means of an equivalent SC circuit, containing ideal components, is presented. The approach is extended by the case of an op-amp with non-switched input SC building blocks.     

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme

This paper describes a 32-KB two-read, one-write ported L0 cache for 4.5-GHz operation in 1.2-V 130-nm dual-V/sub TH/ CMOS technology. The local bitline uses a leakage-tolerant self reverse-bias (SRB) scheme with nMOS source-follower pullup access transistors, while preserving robust full-swing operation. Gate-source underdrive of -220 mV on the bitline read-select transistors is established without external bias voltages or gate-oxide overstress. Device-level measurements in the 130-nm technology show 72/spl times/ bitline active leakage reduction, enabling low-V/sub TH/ usage, 40% bitline keeper downsizing, and 16 bitcells/bitline. 11% faster read delay and 2/spl times/ higher dc noise robustness are achieved compared with high-performance dual-V/sub TH/ bitline scheme. Sustained performance and robustness benefits of the SRB technique against conventional dynamic bitline with scaling to 100- and 70-nm technology is also presented.     

Compact wideband bandpass filter

Designing wideband bandpass filters (BPF) with parallel-coupled microstrip lines requires tight coupling resulting in close separation between the lines and difficulty of fabrication. Here, it is shown that the etched slots in the ground plane of the parallel coupled lines can significantly increase the coupling. This technique has been extended to realize ultra-wideband BPFs having 3-dB fractional bandwidth greater than 100% and low insertion loss in the passband.