The extended quadratic residue code is the only (48,24,12) self-dual doubly-even code

An extremal self-dual doubly-even binary (n,k,d) code has a minimum weight d=4/spl lfloor/n/24/spl rfloor/+4. Of such codes with length divisible by 24, the Golay code is the only (24,12,8) code, the extended quadratic residue code is the only known (48,24,12) code, and there is no known (72,36,16) code. One may partition the search for a (48,24,12) self-dual doubly-even code into three cases. A previous search assuming one of the cases found only the extended quadratic residue code. We examine the remaining two cases. Separate searches assuming each of the remaining cases found no codes and thus the extended quadratic residue code is the only doubly-even self-dual (48,24,12) code.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

Routing Correlated Data with Fusion Cost in Wireless Sensor Networks

In this paper, we propose a routing algorithm called minimum fusion Steiner tree (MFST) for energy efficient data gathering with aggregation (fusion) in wireless sensor networks. Different from existing schemes, MFST not only optimizes over the data transmission cost, but also incorporates the cost for data fusion, which can be significant for emerging sensor networks with vectorial data and/or security requirements. By employing a randomized algorithm that allows fusion points to be chosen according to the nodes' data amounts, MFST achieves an approximation ratio of 5/4log(k + 1), where k denotes the number of source nodes, to the optimal solution for extremely general system setups, provided that fusion cost and data aggregation are nondecreasing against the total input data. Consequently, in contrast to algorithms that only excel in full or nonaggregation scenarios without considering fusion cost, MFST can thrive in a wide range of applications     

Novel method for simultaneous formation of wires and vias of a printed circuit board using nanoporous body

A new type of a flexible printed circuit board with landless vias is developed using a novel method called interconnection via nanoporous structure (INPS). This method can make wires and vias of the printed circuit board simultaneously by a single photo-exposure process. A new photo-induced selective plating method was used to impregnate a nanoporous substrate with copper, and a new photomask was designed, which constitutes of a completely vacant large hole for via and aggregation patterns of very fine holes for wire. Because of the simple process, the INPS board is characterized by landless vias and very fine circuit. Owing to the structure, it is also characterized by flexibility and detachable wires.     

A comparative study of DPSK and OOK WDM transmission over transoceanic distances and their performance degradations due to nonlinear phase noise

We have compared experimentally the transmission performance of return-to-zero differential phase-shift keying (RZ-DPSK) with RZ-ON-OFF keying (OOK), nonreturn-to-zero differential phase-shift keying (NRZ-DPSK), and NRZ-OOK for 100/spl times/10-Gb/s transmission with a spectral efficiency of 0.22 b/s/Hz over transoceanic distances. The Q degradation of the RZ-DPSK after transmission over 9180 km was 3 dB greater than that of RZ-OOK. The experimental results clearly showed the major cause of degradation for DPSK is not cross-phase modulation but self-phase modulation. The calculated nonlinear phase noise, i.e., the Gordon-Mollenauer effect, agreed with the experimental results. A distributed-Raman-amplifier assisted erbium-doped-fiber-amplified transmission line acted well in reducing the nonlinear phase noise.     

Graph-theoretic construction of low-density parity-check codes

This article presents a graph-theoretic method for constructing low-density parity-check (LDPC) codes from connected graphs without the requirement of large girth. This method is based on finding a set of paths in a connected graph, which satisfies the constraint that any two paths in the set are either disjoint or cross each other at one and only one vertex. Two trellis-based algorithms for finding these paths are devised. Good LDPC codes of practical lengths are constructed and they perform well with iterative decoding.     

Extracting Light from Polymer Light‐Emitting Diodes Using Stamped Bragg Gratings

In this paper, we describe a method for increasing the external efficiency of polymer light‐emitting diodes (LEDs) by coupling out waveguided light with Bragg gratings. We numerically model the waveguide modes in a typical LED structure and demonstrate how optimizing layer thicknesses and reducing waveguide absorption can enhance the grating outcoupling. The gratings were created by a soft‐lithography technique that minimizes changes to the conventional LED structure. Using one‐dimensional and two‐dimensional gratings, we were able to increase the forward‐directed emission by 47 % and 70 %, respectively, and the external quantum efficiency by 15 % and 25 %.     

Planar lightwave integrated circuits with embedded actives for board and substrate level optical signal distribution

This paper explores design options for planar optical interconnections integrated onto boards, discusses fabrication options for both beam turning and embedded interconnections to optoelectronic devices, describes integration processes for creating embedded planar optical interconnections, and discusses measurement results for a number of integration schemes that have been demonstrated by the authors. In the area of optical interconnections with beams coupled to and from the board, the topics covered include integrated metal-coated polymer mirrors and volume holographic gratings for optical beam turning perpendicular to the board. Optical interconnections that utilize active thin film (approximately 1-5 /spl mu/m thick) optoelectronic components embedded in the board are also discussed, using both Si and high temperature FR-4 substrates. Both direct and evanescent coupling of optical signals into and out of the waveguide are discussed using embedded optical lasers and photodetectors.