Systematic characterization of Cl2 reactive ion etchingfor improved ohmics in AlGaN/GaN HEMTs

Pre-metal-deposition reactive ion etching (RIE) was performed on an Al_0.3Ga_0.7N/AlN/GaN heterostructure in order to improve the metal-to-semiconductor contact resistance. An optimum AlGaN thickness for minimizing contact resistance was determined. An initial decrease in contact resistance with etching time was explained in terms of removal of an oxide surface layer and/or by an increase in tunnelling current with the decrease of the AlGaN thickness. The presence of a dissimilar surface layer was confirmed by an initial nonuniform etch depth rate. An increase in contact resistance for deeper etches was experienced. The increase was related to depletion of the two-dimensional (2-D) electron gas (2-DEG) under the ohmics. Etch depths were measured by atomic force microscopy (AFM). The contact resistance decreased from about 0.45 Ωmm for unetched ohmics to a minimum of 0.27 Ωmm for 70 Å etched ohmics. The initial thickness of the AlGaN layer was 250 Å. The decrease in contact resistance, without excessive complications on device processing, supports RIE etching as a viable solution to improve ohmic contact resistance in AlGaN/GaN HEMTs     

AGE method simulations of a turbulent far‐wake compared to spectral DNS

Turbulent flow simulation methods based on finite differences are attractive for their simplicity, flexibility and efficiency, but not always for accuracy or stability. This paper demonstrates that a good compromise is possible with the advected grid explicit (AGE) method. Starting from the same initial field as a previous spectral DNS, AGE method simulations of a planar turbulent wake were carried out as DNS, and then at three levels of reduced resolution. The latter cases were in a sense large‐eddy simulations (LES), although no specific sub‐grid‐scale model was used. Results for the two DNS methods, including variances and power spectra, were very similar, but the AGE simulation required much less computational effort. Small‐scale information was lost in the reduced resolution runs, but large‐scale mean and instantaneous properties were reproduced quite well, with further large reductions in computational effort. Quality of results becomes more sensitive to the value chosen for one of the AGE method parameters as resolution is reduced, from which it is inferred that the numerical stability procedure controlled by the parameter is acting in part as a sub‐grid‐scale model. Copyright © 2002 John Wiley & Sons, Ltd.     

Half-bridge inverter using 4H-SiC gate turn-off thyristors

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm²) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V/μs in these devices     

Nonlinear Theory of Spectra of Thermally Stimulated Currents in Complex Crystals with Hydrogen Bonds

The nonlinear theory of thermally stimulated depolarization currents is developed. The theory explains the processes of hetero- and homocharge relaxation in complex crystals with hydrogen bonds and allows the relaxation oscillator parameters to be calculated using the quadratic approximation for the external electric field.     

Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.     

Diagnosis and Consulting for Control Network Performance Engineering of CSMA-Based Networks

Network performance engineering can verify the design and dimensioning of large-scale control networks like CSMA-based building automation networks. It combines performance analysis with diagnosis methods to evaluate the network utilization and to detect design errors before installation and can therewith save the expenses of overdimensioning and redesign. This paper will develop a diagnosis model based on fault trees that is able to use the huge amount of performance analysis results to identify design errors and analyze their coherences. This enables not only a fast tracing back of fault causes and the derivation of solutions; it can also visualize the fault coherence to the user and help him to understand his design. Additional consulting tools implement best practice strategies, to support the user in parameterization.     

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.