Stability of a laminar boundary layer flowing along a concave surface with uniform mainstream velocity

Predictions, by the Galerkin method, are presented of the stability of three-dimensional disturbances in laminar boundary-layer flow at zero pressure gradient along a concave surface. The analysis confirms Meksyn's finding of more than one critical state; predictions for the first agree with those of Kahawita and Meroney at low Goertler number G and with the vortex amplification predictions of Smith at high G. Both the first and second critical states have G values below those of Meksyn; the amplification field of the second, however, encompasses the range of available measurements, and therein, has dimensionless vortex energy levels only half those of the first. The plausibility of least vortex energy as a determining factor in favour of the second critical field is further strengthened by its limited G range, the upper limit of about 7 corresponding closely to Liepmann's observations^4,5 of the onset of transition to turbulence. These findings are almost insensitive to mainstream Mach numbers up to 0.9, stagnation conditions up to 15 bar and 1200 K, and Reynolds numbers from 2000 to 6000 based on boundary layer thickness     

Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications     

Systematical changes in diffraction efficiencies through Ag-photodoping into amorphous GeSe thin films

It is well known that the phenomenon of Ag-photodoping into amorphous (a-) chalcogenide film depends on film thickness (d). Herein, we report that the effects of Ag-photodoping into a-GeSe thin films exhibit a systematical change dependent on d using a holographic exposure (HeCd laser) and the measurement of diffraction efficiency (η) in real time. The η-kinetics of Ag-photodoping in the sample structure of an a-GeSe/Ag/p-type Si substrate is divided into two steps. A photodarkening-dominant process related to the generation of valence-alternation pairs (VAPs) in the chalcogenide explains the first step while a doping-dominant process accounts for the second step. In particular, we confirmed that the d-dependencies of the η-kinetics are classified into 3 groups: (A) d < 2d_P; (B) 2d_P ? d < 4d_P; (C) d > 4d_P, where d_P indicates the penetration depth of the HeCd laser. In group A, the Ag-doping process occurs simultaneously with the darkening process. In group C, the η-kinetics results from the darkening process only. Contrarily, in group B, the η-kinetics exhibits a sharp distinction between the photodarkening process and the Ag-doping process, and in particular, η_M increases almost linearly with an increase in d.     

E-mode cutoff wave number of circular waveguide loaded with dielectric sector

The E-mode cutoff wave numbers of circular waveguide loaded with dielectric sectors were evaluated theoretically using the null-field formulation. These values are found to agree closely with cutoff wave numbers measured by using the transverse resonance technique.<>     

10 Gb/s Linear Full-Rate CMOS Phase Detector for Clock Data Recovery Circuit

An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.     

Effective method for preparation of oxide-free Ge2Sb2Te5 surface: An X-ray photoelectron spectroscopy study

Cleaning the surfaces of the as-deposited Ge₂Sb₂Te₅ was studied by X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM) and X-ray diffraction (XRD). The mixed native oxides on the as-deposited Ge₂Sb₂Te₅ surface can be easily removed by dipping Ge₂Sb₂Te₅ in de-ionized water for 1 min, while the surface morphology remains unchanged after cleaning. Native oxides only re-grow after exposure to air for more than 4 min. Although dipping in water leads to a surface layer deficient in Ge and Sb, the surface composition of Ge₂Sb₂Te₅ can recover to its stoichiometric value after annealing at 200 °C in vacuum. The phase remains amorphous at room temperature after dipping in water, and changes to fcc and hcp after annealing at 100 and 220 °C, respectively.     

Three-dimensional interconnect for multilayer module packages with selectively anodised aluminium substrate

It is reported that 3-D interconnects fabricated with a selectively anodised aluminium process for a multilayer module package can be used to evaluate high-frequency performance. The proposed method of fabricating vertical interconnects is easier and more cost-effective than other RF MEMS processes. To transfer RF signals vertically, coaxial hermetic seal vias with characteristic 50 Omega impedances and embedded anodised aluminium vias with a solder ball attachment and flip-chip bonding were used. The optimised interconnect structure demonstrated RF characteristics with an insertion loss of less than 1.55 OmegadB and a return loss of less than 12.25 OmegadB over a broad bandwidth ranging from 0.1 to 10 OmegaGHz. Experimental results suggest that the developed technology, which is based on selectively anodised aluminium, can be applied to new 3-D packaging solutions.     

Regularized field map estimation in MRI

In fast magnetic resonance (MR) imaging with long readout times, such as echo-planar imaging (EPI) and spiral scans, it is important to correct for the effects of field inhomogeneity to reduce image distortion and blurring. Such corrections require an accurate field map, a map of the off-resonance frequency at each voxel. Standard field map estimation methods yield noisy field maps, particularly in image regions with low spin density. This paper describes regularized methods for field map estimation from two or more MR scans having different echo times. These methods exploit the fact that field maps are generally smooth functions. The methods use algorithms that decrease monotonically a regularized least-squares cost function, even though the problem is highly nonlinear. Results show that the proposed regularized methods significantly improve the quality of field map estimates relative to conventional unregularized methods.      

Consideration of temperature and current stress testing on flip chip solder interconnects

This work discusses the experimental set-up and data interpretation for high temperature and current stress tests of flip chip solder joints using the four-point Kelvin measurement technique. The single solder joint resistance responses are measured at four different four-point Kelvin structure locations in a flip chip package. Various temperatures (i.e., 125–165 °C) and electric current (i.e., 0.6–1.0 A) test conditions are applied to investigate the solder joint resistance degradation behavior and its failure processes. Failure criterion of 20% and 50% joint resistance increases, corresponding to solder and interfacial voiding, are employed to evaluate the solder joint electromigration reliability. The absolute resistance value is substantially affected by the geometrical layout of the metal lines in the four-point Kelvin structure, and this is confirmed by finite element simulation.Different current flow directions and strengths yielded different joint resistance responses. The anode joint, where electrons flow from the die to the substrate, usually measured an earlier resistance increase than the cathode joint, where electrons flow in the opposite direction. The change in measured joint resistances can be related to solder and interfacial voiding in the solder joint except for ±1 A current load, where resistance drop mainly attributed to the broken substrate Cu metallization as a result of “hot-spot” phenomenon. The solder joint temperature increases above the oven ambient temperature by ～25 °C, ～40 °C and ～65 °C for 0.6 A, 0.8 A and 1.0 A stress current, respectively. It is found that two-parameter log-normal distribution gives a better lifetime data fitting than the two-parameter Weibull distribution. Regardless of failure criterion used, the anode joint test cells usually calculated a shorter solder joint mean life with a lower standard variation of 0.3–0.6, as compared to the cathode joint test cells with a higher standard variation of 0.8–1.2. For a typical flip chip solder joint construction, electromigration reliability is mainly determined by the under bump metallization consumption and dissolution, with intermetallic compound formation near the die side of an anode joint.