Strongly Modular Subgroup in Finite Group

Ｓｔｒｏｎｇｌｙ　Ｍｏｄｕｌａｒ　Ｓｕｂｇｒｏｕｐ　ｉｎ　Ｆｉｎｉｔｅ　ＧｒｏｕｐＳｔｒｏｎｇｌｙＭｏｄｕｌａｒＳｕｂｇｒｏｕｐｉｎＦｉｎｉｔｅＧｒｏｕｐ￥ＹｕＪｉａｎｌｉ；ＪｉａｏＤｏｎｇｗｕ（ＬｕｏｙａｎｇＩｎｓｔｉｔｕｔｅｏｆＴｅｃｈｎｏｌｏｇ...     

AlGaAs／AlAs体系DBR的MOCVD生长及表征

设计并利用MOCVD在（311）GaAs衬底上生长了12．5个周期的Al0．6Ga0．4As／AlAs黄绿光分布式Bragg反射（DBR）体系，测量了白光反光谱及其外延片峰值波长分布，反射率90％以上，波长不均匀性在1．0％以下；利用了X射线双晶衍射对其进行结构表征，580nm波长DBR结构周期为84．5nm。     

基于进行计算设计无法的完全重构两通道滤波器组

该文提出了一种设计无乘法完全重构的两通道滤波器组的方法。这种滤波器组在基于对提升模式结构改进的研究成果之上,提出了给定初始值的进化计算搜索设计方法。这种设计方法具有比用遗传算法快的特点。文中详细描述了此算法的过程,并给出了设计例子和结果。     

Sensitivity analysis of multiconductor transmission lines andoptimization for high-speed interconnect circuit design

Sensitivity analysis of multiconductor transmission lines is derived from a new, all-purpose multi-conductor transmission line model in both frequency domain and time domain. Computer implementation of this new model as well as the sensitivity analysis has been completed. It enables efficient, accurate simulations of interconnect circuit responses as well as sensitivity analysis with respect to both electrical and physical transmission line parameters. By applying sensitivity analysis to high-speed interconnect circuit design, design variables are optimized to achieve simultaneous minimization of crosstalk, delays and reflections at desired nodes in the circuit without violating any indispensable design rules. Numerical examples are presented to demonstrate the validity of the proposed sensitivity analysis and illustrate its application to the optimization of high-speed interconnect circuit design     

终端靶场中相位畸变对近场光束质量的影响

终端靶场聚焦系统中的光学元件上存在不可避免的缺陷致使光场波前发生畸变,根据高功率激光装置终端靶场系统中强光束传输的特点,建立了描述光学元件引入的局域相位调制的模型,研究了终端靶场中具有高斯型相位波前畸变的平顶光束经过透镜会聚,并在后续防溅射板等熔石英介质中经历非线性增长的传输演变过程,详细分析了高斯型相位波前畸变、熔石英厚度和透镜焦距对终端靶场聚焦系统中的近场光束质量的影响。结果表明,高斯型波前畸变越严重、熔石英厚度越长、透镜焦距越短,近场光束质量越差,中高频增长越多。     

电工及电子技术教学探讨

本文以培养学生创造性思维为目标,优化教学内容,结合现代化教学手段,理论联系实践,增加基础性实验,提高学生学习能力和综合能力,在非电类专业电工及电子技术教学改革中做了一些尝试。     

基于宽窄带功率比值法的GNSS载噪比估计改进方法

为了降低载噪比估计算法的实现复杂度,提出了一种改进的宽窄带载噪比估计方法。该方法利用接收机良好跟踪信号时信号能量主要分布在I支路这一特点,将传统的宽窄带功率比值法中的宽带进行简化变为仅取I支路信号,而窄带保持不变来进行载噪比估计。在详细推导了改进后算法的载噪比估计的理论表达式后,通过仿真测试进行了验证与分析,最后对K值的选取进行了讨论。测试结果表明,改进后的算法与传统算法的性能基本相当,但相比传统的宽窄带功率比值法而言,在算法复杂度方面加法和乘法次数都减少了1000次左右,约为传统算法的60%,使算法复杂度得到了有效降低。     

Instrumentation-Driven Validation of Dataflow Applications

Dataflow modeling offers a myriad of tools for designing and optimizing signal processing systems. A designer is able to take advantage of dataflow properties to effectively tune the system in connection with functionality and different performance metrics. However, a disparity in the specification of dataflow properties and the final implementation can lead to incorrect behavior that is difficult to detect. This motivates the problem of ensuring consistency between dataflow properties that are declared or otherwise assumed as part of dataflow-based application models, and the dataflow behavior that is exhibited by implementations that are derived from the models. In this paper, we address this problem by introducing a novel dataflow validation framework (DVF) that is able to identify disparities between an application’s formal dataflow representation and its implementation. DVF works by instrumenting the implementation of an application and monitoring the instrumentation data as the application executes. This monitoring process is streamlined so that DVF achieves validation without major overhead. We demonstrate the utility of our DVF through design and implementation case studies involving an automatic speech recognition application, a JPEG encoder, and an acoustic tracking application.     

基于瑞利散射的单端BOTDA系统温度特性研究

提出一种不受电光调制器传输曲线温度漂移现象影响的基于瑞利散射的单端布里渊光时域分析系统,并对系统所需的合成信号及温度特性进行分析,通过搭建单端布里渊光时域分析温度传感系统测量系统的温度特性.结果表明:通过测量布里渊增益谱获得的布里渊频移与温度呈良好的线性关系;由单端布里渊光时域分析温度测量系统获得的布里渊频移的温度系数为1.109 MHz/℃,与传统双端布里渊光时域分析系统获得的1.20 MHz/℃具有良好的一致性,在1.77 km光纤上可实现9.5m空间分辨率的温度传感测量.     

Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

r of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level.Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.