1,3-dipolar cycloaddition as a method for synthesis of fullerene C60 derivatives containing heterocyclic moieties

We generalize literature data and our own experimental data on using 1,3-dipolar cycloaddition reactions for synthesis of fullerene C₆₀ derivatives containing annelated heterocyclic moieties.M. V. Lomonosov Moscow State University, Moscow 119899, Russia. Translated from Khimiya Geterotsiklicheskikh Soedinenii, No. 3, pp. 291–297, March, 1998.     

Performance of interface engineeredSiNx/ICL/InP/In0.53Ga0.47As/InP dopedchannel HIGFET's

SiN_x/InP/InGaAs doped channel passivated heterojunction insulated gate field effect transistors (HIGFETs) have been fabricated for the first time using an improved In-S interface control layer (ICL). The insulated gate HIGFETs exhibit very low gate leakage (10 nA@V_GS =±5 V) and I_DS (sat) of 250 mA/mm. The doped channel improves the DC characteristics and the HIGFETs show transconductance of 140-150 mS/mm (L_g=2 μm), f_t of 5-6 GHz (L_g=3 μm), and power gain of 14.2 dB at 3 GHz. The ICL HIGFET technology is promising for high frequency applications     

Parallel reduced area multipliers

As developed by Wallace and Dadda, a method for high-speed, parallel multiplication is to generate a matrix of partial products and then reduce the partial products to two numbers whose sum is equal to the final product. The resulting two numbers are then summed using a fast carry-propagate adder. This paper presents Reduced Area multipliers, which employ a modified reduction scheme that results in fewer components and less interconnect overhead than either Wallace or Dadda multipliers. This reduction scheme is especially useful for pipelined multipliers, because it minimizes the number of latches required in the reduction of the partial products. The reduction scheme can be applied to either unsigned (sign-magnitude) or two's complement numbers. Equations are given for determining the number of components and a method is presented for estimating the interconnect overhead for Wallace, Dadda, and Reduced Area multipliers. Area estimates indicate that for non-pipelined multipliers, the reduction in area achieved with Reduced Area multipliers ranges from 3.7 to 6.6 percent relative to Dadda multipliers, and from 3.8 to 8.4 percent relative to Wallace multipliers. For fully pipelined multipliers, the reduction in area ranges from 15.1 to 33.6 percent relative to Dadda multipliers, and from 2.9 to 9.0 percent relative to Wallace multipliers.     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

LEICA: a low energy ion composition analyzer for the study of solarand magnetospheric heavy ions

The SAMPEX (Solar, Anomalous, and Magnetospheric Particle Explorer) LEICA instrument is designed to measure ~0.5-5-MeV/nucleon solar and magnetospheric ions over the range from He-Ni. The instrument is a time-of-flight (TOF) mass spectrometer, which measures particle TOF over an ~0.5-m path and the residual energy deposited in an array of Si solid state detectors. Large-area microchannel plates are used, resulting in a large geometrical factor for the instrument (0.6 cm² sr), which is essential for accurate compositional measurements in small solar flares and in studies of precipitating magnetospheric heavy ions     

Development of a distributed sensing technique using Brillouinscattering

This paper reviews the developments of a distributed strain and temperature sensing technique that uses Brillouin scattering in single-mode optical fibers. This technique is based on strain- and temperature-induced changes in the Brillouin frequency shift. Several approaches for measuring the weak Brillouin line are compared     

Analysis and design-optimization of LCC resonant inverter forhigh-frequency AC distributed power system

The analysis and design of an LCC resonant inverter for a 20 kHz AC distributed power system are presented. Several resonant converter topologies are assessed to determine their suitability for high efficiency power conversion, under resistive and reactive loads. Two LCC-resonant inverter designs were implemented. One with all switches operating with zero voltage switching (ZVS), and another with two switches operating with ZVS and two switches with zero current switching (ZCS). The experimental results are presented along with a performance comparison of the two versions     

Analysis of aperture-coupled microstrip antenna using thesegmentation method

The authors present an original analysis of an aperture-coupled microstrip antenna. The theory is based on the segmentation method, which considers the patch as a multiport network whose impedance matrix is deduced from a hybrid matrix, and the use of analytical expressions of the cavity admittance at the slot centre. The theory is presented for the first time, and the theoretical results are in good agreement with previous published measurements     

Tri-band frequency selective surface with circular ring elements

Theoretical analysis, physical reasonings, and experimental verifications are presented for a frequency selective surface with circular ring elements. Both double-screen and single-screen designs are generated for a tri-band system that reflects the X-band signal while transmitting through the S- and Ku-band signals. In these designs, the dielectric loading effect is used to reduce ring size and element spacing and thus avoid the grating lobe problem. The circular ring element is very insensitive to a large variation of the RF incident angle