Quadrature Mismatch Shaping for Digital-to-Analog Converters

Quadrature sigma-delta analog-to-digital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digital-to-analog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance. This paper proposes new quadrature bandpass (QBP) mismatch shaping techniques. In our approach, the I and Q DACs are merged into one complex DAC, which leads to near-perfect I/Q balance. To select the unit DAC elements of the complex multibit DAC, the well-known butterfly shuffler and tree structure are generalized towards a complex structure, and necessary constraints for their correct functioning are derived. Next, a very efficient first-order QBP shaper implementation is proposed. Finally, the newly presented complex structures are simulated to prove their effectiveness and are compared with each other with respect to performance     

Estimating and reducing the memory requirements of signal processing codes for embedded systems

Most embedded systems have limited amount of memory. In contrast, the memory requirements of the digital signal processing (DSP) and video processing codes (in nested loops, in particular) running on embedded systems is significant. This paper addresses the problem of estimating and reducing the amount of memory needed for transfers of data in embedded systems. First, the problem of estimating the region associated with a statement or the set of elements referenced by a statement during the execution of nested loops is analyzed. For a fixed execution ordering, a quantitative analysis of the number of elements referenced is presented; exact expressions for uniformly generated references and a close upper and lower bound for nonuniformly generated references are derived. Second, in addition to presenting an algorithm that computes the total memory required, this paper also discusses the effect of transformations (that change the execution ordering) on the lifetimes of array variables, i.e., the time between the first and last accesses to a given array location. The term maximum window size is introduced, and quantitative expressions are derived to compute the maximum window size. A detailed analysis of the effect of unimodular transformations on data locality, including the calculation of the maximum window size, is presented.     

Bandpass filters with reconfigurable transmission zeros using varactor-tuned tapped stubs

In this letter, bandpass filters with one or two tunable transmission zeros are proposed. The reconfigurable transmission zeros are implemented through varactors in combination with tapped quarter-wavelength stubs. Based on mixed mode simulations including EM simulation and circuit simulation, the proposed filters were designed and fabricated on low-cost FR4 board. The measurement results verified the design concepts.     

Nash equilibria of packet forwarding strategies in wireless ad hoc networks

In self-organizing ad hoc networks, all the networking functions rely on the contribution of the participants. As a basic example, nodes have to forward packets for each other in order to enable multihop communication. In recent years, incentive mechanisms have been proposed to give nodes incentive to cooperate, especially in packet forwarding. However, the need for these mechanisms was not formally justified. In this paper, we address the problem of whether cooperation can exist without incentive mechanisms. We propose a model,based on game theory and graph theory to investigate equilibrium conditions of packet forwarding strategies. We prove theorems about the equilibrium conditions for both cooperative and noncooperative strategies. We perform simulations to estimate the probability that the conditions for a cooperative equilibrium hold in randomly generated network scenarios.. As the problem is involved, we deliberately restrict ourselves to a static configuration. We conclude that in static ad hoc networks where the relationships between the nodes are likely to be stab le-cooperation needs to be encouraged.     

Computation of Running Averages

This brief presents and compares several recursive and nonrecursive techniques for the efficient computation of the running average of discrete signals. First of all, the standard recursive algorithm is considered and its long-term accuracy is assessed when the floating-point arithmetic is employed. A cheap refreshing strategy is proposed as a means of keeping the computed value close enough to the exact one. Then, two alternative nonrecursive algorithms, requiring only log₂N additions, are developed, which are as reliable and accurate as the direct implementation     

High Rate Data Synchronization in GALS SoCs

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner     

Equivalent electrical network of the DNA molecule

The variation of current density with bias or temperature is examined for DNA molecules of different configuration. To this end, the DNA molecule is represented as an equivalent electrical network whose behavior is then simulated with PSPICE. The results are found to be in close agreement with ones obtained within a physical model. It is established that the electrical response of a DNA molecule to an applied electric field depends on the boundary conditions and the potential profile along the molecule. This finding should contribute to the creation of a complete library of DNA-molecule configurations with prescribed electrical properties.     

All-optical seed pulse extraction for packet synchronization based on self-induced effects in a vertical-cavity semiconductor gate

Self-induced effects in a passive polarization-independent vertical-cavity semiconductor gate are investigated numerically and experimentally. We demonstrate all-optical seed-pulse extraction for synchronization of differential phase-shift keying and ON-OFF keying packets at 10 Gb/s. Our results provide evidence that vertical-cavity gates, exploiting saturable absorption in semiconductor quantum-wells, exhibit attractive performances in terms of efficiency, power consumption, and polarization independency.     

The colored revolution of bioimaging

This paper provides an overview of the main aspects of modern fluorescence microscopy. It covers the principles of fluorescence and highlights the key discoveries in the history of fluorescence microscopy. The paper also discusses the optics of fluorescence microscopes and examines the various types of detectors. It also discusses the signal and image processing challenges in fluorescence microscopy and highlights some of the present developments and future trends in the field.     

可重定位的基于事务的系统级验证

功能验证已经成为开发SoC的主要问题。随着一些复杂SoC的规模超过两千万门，以及对开发和集成嵌入式软件的需求持续增加，软件模拟器已经力所不及。在设计过程需要几百万个时钟周期来充分测试和验证软件功能的情况下，软件仿真器的性能下降到1-5Hz。按照这种速率，软件调试需要几年的时