State of polarization changes: Classification and measurement

We propose a standardization procedure that provides a convenient, quantitative and reproducible laboratory-based method for measuring the state of polarization (SOP) fluctuations produced by polarization varying devices. This method is based on the SOP distributions generated by commercial polarization scramblers. We show that these devices generate distributions of the maximum change of the SOP (in a given sample time) that follow Rayleigh statistics, which scale linearly with scrambling frequency and the sample time. We use this procedure to measure the SOP fluctuations in a short length of coiled fiber subject to mechanical perturbations.     

Nonlinearity analysis and optimization of HBTs for optical mixer designs

Two types of photo heterojunction bipolar transistor (HBT) to directly down-convert optical signals to electronic signals have been reported in the literature: a conventional photo-HBT in which light penetrates through the area of the base-collector junction and an HBT where light shines through the base-collector edge for higher conversion efficiency. Although the performance in relation to bias conditions has been published, the detailed analyses for identifying the parameters and bias conditions that provide optimum direct down-conversion have not been examined. This paper provides a full explanation of the operation of the down-conversion for both HBT configurations based on low-frequency analyses. Such information is useful for both understanding the nonlinear mechanisms involved and designing for maximum efficiency. In addition, a new circuit has been developed from the basic HBT down-conversion circuit that provides improved performance.     

Switched-Current Filters Revisited: Square-Root Domain Sampled-Data Filters

In this brief, the well-known switched-current (SI) filtering technique is revisited using the concept of the square-root domain (SRD) filtering. It is proved that SI filters are a subclass of the SRD filters, where sampled-data signal processing is performed. This is achieved by considering typical lossless and lossy SRD sampled-data integrator configurations, using a set of complementary SRD operators which are based on the quadratic I-V relationship of MOS transistor operated in the saturation. Circuit examples are given, where linear-domain integrator and third-order filter configurations were derived using appropriate SRD sampled-data building blocks     

Training and optimization of an artificial neural network controlling a hybrid power filter

A hybrid power compensator (HPC) consisting of a static VAr compensator and a dynamic compensator needs to be optimally controlled during the compensation of nonlinear loads. The HPC must be controlled to meet minimum requirements in terms of power factor and harmonic distortion, while at the same time minimizing its total cost. An artificial neural network (ANN) is used to control the HPC amidst a very dynamic power system environment. The performance of a reference ANN is evaluated while controlling an HPC connected to a typical nonlinear industrial load. The training and performance of the ANN is then optimized in terms of training set size, training set packing and ANN topology and the performance compared to the reference ANN. This paper highlights the importance of optimising the mentioned ANN parameters to achieve optimum ANN training and modeling accuracy. The results obtained reveals that the application of an ANN in controlling an HPC is feasible given that the ANN parameters are chosen appropriately.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs

The hydrogen annealing process has been used to improve surface roughness of the Si-fin in CMOS FinFETs for the first time. Hydrogen annealing was performed after Si-fin etch and before gate oxidation. As a result, increased saturation current with a lowered threshold voltage and a decreased low-frequency noise level over the entire range of drain current have been attained. The low-frequency noise characteristics indicate that the oxide trap density is reduced by a factor of 3 due to annealing. These results suggest that hydrogen annealing is very effective for improving device performance and for attaining a high-quality surface of the etched Si-fin.     

Analysis of feedback for higher order polarization-mode dispersion mitigation of NRZ 40-Gb/s optical transmission

First-order polarization-mode dispersion (PMD) compensation by means of a polarization controller and a differential delay line is not sufficient to guarantee error-free transmission for 40-Gb/s channels when higher order effects severely increase signal distortion. Higher order mitigation is possible by cascading more than one first-order block. However, only two-stage or three-stage devices remain simple enough to be actually controlled. The performance of such higher order PMD compensators is evaluated by means of numerical simulations. Two different feedback signals have been used, demonstrating that first-order and higher order PMD distortion of nonreturn-to-zero (NRZ) pulses at 40 Gb/s can be strongly mitigated for instantaneous values of the differential group delay (DGD) up to the bit slot, when the compensator is properly controlled.