A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.     

Reducing CIC filter complexity

This paper provides several tricks to reduce the complexity and enhance the usefulness of cascaded integrator-comb (CIC) filters. The first trick shows a way to reduce the number of adders and delay elements in a multi-stage CIC interpolation filter. The result is a multiplierless scheme that performs high-order linear interpolation using CIC filters. The second trick shows a way to eliminate the integrators from CIC decimation filters. The benefit is the elimination of unpleasant data word growth problems.     

A New Hand-Held Microsystem Architecture for Biological Analysis

This paper presents a hand-held microsystem based on new fully integrated magnetoresistive biochips for biomolecular recognition (DNA hybridization, antibody antigen interaction, etc.). Magnetoresistive chip surfaces are chemically treated, enabling the immobilization of probe biomolecules such as DNA or antibodies. Fluid handling is also integrated in the biochip. The proposed microsystem not only integrates the biochip, which is an array of 16times16 magnetoresistive sensors, but it also provides all the electronic circuitry for addressing and reading out each transducer. The proposed architecture and circuits were specifically designed for achieving a compact, programmable and portable microsystem. The microsystem also integrates a hand-held analyzer connected through a wireless channel. A prototype of the system was already developed and detection of magnetic nanoparticles was obtained. This indicates that the system may be used for magnetic label based bioassays     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.     

The effect of photon energy and temperature on the persistent tunneling photoconductivity effect in Al/δ(Si)-GaAs structures

The phenomenon of persistent tunneling photoconductivity was studied using the tunneling spectroscopy technique at liquid-helium temperature: the separation between the unoccupied levels in a δ-doped layer at the GaAs surface decreased after illumination. This decrease was due to an increase in the width of the quantum well of the δ-doped layer. For photon energies hv exceeding the GaAs band gap E _g , this increase in the width of the quantum well was related to the accumulation of positive charge in the depth of GaAs induced by the generation of the electron-hole pairs and photoionization of deep centers. For hv < E _g (including the case of CO₂ laser), only photoionization is important. The experimental data agree with the self-consistent calculations. The critical temperature for the effect has been determined (T _c = 45 K); at higher temperatures, the effect disappears.     

Finite sample size effect on minimum variance beamformers: optimum diagonal loading factor for large arrays

Minimum variance beamformers are usually complemented with diagonal loading techniques in order to provide robustness against several impairments such as imprecise knowledge of the steering vector or finite sample size effects. This paper concentrates on this last application of diagonal loading techniques, i.e., it is assumed that the steering vector is perfectly known and that diagonal loading is used to alleviate the finite sample size impairments. The analysis herein is asymptotic in the sense that it is assumed that both the number of antennas and the number of samples are high but have the same order of magnitude. Borrowing some results of random matrix theory, the authors first derive a deterministic expression that describes the asymptotic signal-to-noise-plus-interference ratio (SINR) at the output of the diagonally loaded beamformer. Then, making use of the statistical theory of large observations (also known as general statistical analysis or G-analysis), the authors derive an estimator of the optimum loading factor that is consistent when both the number of antennas and the sample size increase without bound at the same rate. Because of that, the estimator has an excellent performance even in situations where the quotient between the number of observations is low relative to the number of elements of the array.     

Controlled elements for designing ciphers suitable to efficient VLSI implementation

This work considers the problem of increasing the performance of the ciphers based on Data-Dependent (DD) operations (DDO) for VLSI implementations. New minimum size primitives are proposed to design DDOs. Using advanced DDOs instead of DD permutations (DDP) in the DDP-based iterative ciphers Cobra-H64 and Cobra-H128 the number of rounds has been significantly reduced yielding enhancement of the “performance per cost” value and retaining security at the level of indistinguishability from a random transformation. To obtain further enhancement of this parameter a new crypto-scheme based on the advanced DDOs is proposed. The FPGA implementation of the proposed crypto-scheme achieves higher throughput value and minimizes the allocated resources than the conventional designs. Design of the DDO boxes of different orders is considered and their ASIC implementation is estimated.     

Nonlinearity analysis and optimization of HBTs for optical mixer designs

Two types of photo heterojunction bipolar transistor (HBT) to directly down-convert optical signals to electronic signals have been reported in the literature: a conventional photo-HBT in which light penetrates through the area of the base-collector junction and an HBT where light shines through the base-collector edge for higher conversion efficiency. Although the performance in relation to bias conditions has been published, the detailed analyses for identifying the parameters and bias conditions that provide optimum direct down-conversion have not been examined. This paper provides a full explanation of the operation of the down-conversion for both HBT configurations based on low-frequency analyses. Such information is useful for both understanding the nonlinear mechanisms involved and designing for maximum efficiency. In addition, a new circuit has been developed from the basic HBT down-conversion circuit that provides improved performance.     

On-demand learning for a wireless campus

The current Internet and wireless networks are harsh environments for transporting high-bandwidth multimedia data. We examine the technical issues involved, and describe an end-to-end solution to support a Web-based learn-on-demand system that operates in a wireless campus environment.     

Asymptotic performance of single parity-check product codes

This article investigates the asymptotic performance of single parity-check (SPC) product codes (PCs) from a decoding point of view. Specifically, the probability of bit error is bounded before and after the decoding of each dimension, similar to the analysis of "iterated codes" by Elias (1954). It is shown that the asymptotic probability of bit error can be driven to zero as the number of dimensions, and hence the block length, increases at signal-to-noise ratios (SNRs) within 2 dB of capacity over the additive white Gaussian noise (AWGN) channel.