A fast motion estimation algorithm based on the block sum pyramid

In this correspondence, a fast approach to motion estimation is presented. The algorithm uses the block sum pyramid to eliminate unnecessary search positions. It first constructs the sum pyramid structure of a block. Successive elimination is then performed hierarchically from the top level to the bottom level of the pyramid. Many search positions can be skipped from being considered as the best motion vector and, thus, the search complexity can be reduced. The algorithm can achieve the same estimation accuracy as the full search block matching algorithm with much less computation time.     

Parallel BIST architecture for CAMs

A new parallel test algorithm and a built-in self test (BIST) architecture for efficient testing of various types of functional faults in content addressable memories (CAMs) are developed. The results show that efficient and practical testing with very low complexity and area overhead can be achieved     

Simple approximations of the DC flux influence on the core losspower electronic ferrites and their use in design of magnetic components

The effect of DC flux on the core loss is examined for the practical range of power and frequency. Relevant core loss equations are derived and applied to an optimization algorithm to determine the minimum core loss at a given ratio of s (DC flux density to AC peak flux density). It has been found that the curves of hysteresis loss density versus the ratio of s exhibit a peak at a critical ratio. Below or above this critical ratio, the loss density decreases drastically. On the other hand, the curves of eddy-current loss density versus the ratio of s exhibits a minimum point at a critical ratio. Below or above this critical ratio, the loss density increases gradually     

Solving the gate packing problem using a concurrent network

The layout problem of gate matrices and one-dimensional logic arrays is composed of two major tasks: to find a permutation of gates which minimises the number of tracks required and to layout/pack gates based on the ordering. A parallel algorithm is presented which can pack n gates within O(1) time, whereas the conventional near-optimum algorithm needs O(n/sup 2/) time. The simulation results show that the increase of the problem size does not degrade the solution quality.<>     

On detecting the presence of fetal R-wave using the moving averagedmagnitude difference algorithm

An efficient algorithm detecting the presence of a fetal QRS complex is presented. The proposed fetal QRS detection method computes the averaged magnitude of the difference between the fetal ECG signal and the reference signal to detect the fetal QRS event. The detected fetal QRS complexes are exponentially averaged to generate the template signal which can track the slowly varying shape of the fetal ECG signal. As an effort to obtain improved detection performances, two approaches of normalizing the fetal ECG signal and the template are considered.     

Control of circulating current in two parallel three-phase boost rectifiers

One unique feature in parallel three-phase converters is a potential zero-sequence circulating current. To avoid the circulating current, most present technology uses an isolation approach, such as transformers or separate power supplies. This paper proposes a parallel system where individual converters connect both AC and DC sides directly without additional passive components to reduce size and cost of the overall parallel system. In this case, the control of the circulating current becomes an important objective in the converter design. This paper: (1) develops an averaged model of the parallel converters based on a phase-leg averaging technique; (2) a zero-sequence model is then developed to predict the dynamics of the zero-sequence current; (3) based on the zero-sequence model, this paper introduces a new control variable, which is associated with space-vector modulation; (4) a strong zero-sequence current control loop is designed to suppress the circulating current; and (5) simulation and experimental results validate the developed model and the proposed control scheme.     

Emission and sputtering characteristics of Ne-Ar mixed gas glow discharge plasmas.

The emission characteristics of several Cu lines emitted from a Ne-Ar mixed gas glow discharge plasma were investigated. The addition of small amounts of Ar to a Ne plasma increases the sputtering rate of a Cu sample because Ar ions, which work as the impinging ions for cathode sputtering, are predominantly produced through Penning ionization collisions between Ne metastables and Ar atoms. Ar addition also elevates the number density of electrons in the plasma. These changes occurring in the Ne-Ar mixed gas plasma result in enhanced emission intensities of the Cu lines. The Cu II 270.10-nm and the Cu II 224.70-nm lines yield different intensity dependence on the Ar partial pressure added. This phenomenon is because these Cu II lines are excited principally through different charge transfer processes: collisions with Ne ions for the Cu II 270.10-nm line and collisions with Ar ions for the Cu II 224.70-nm line. The shape of sputtered craters in the Ne-Ar glow discharge plasma was measured. The depth resolution was improved when Ar was added to a Ne plasma because the crater bottoms were flatter with larger Ar partial pressures.     

The effects of carrier-velocity saturation on high-current BJToutput resistance

Modern bipolar junction transistors (BJTs) tend to operate with saturated carrier velocity in the collector space-charge region. A physical analysis of the effects of velocity saturation on the output resistance of BJTs, especially for high current levels is presented. Physical analyses show that when the collector current density approaches a critical value, the Early voltage can increase significantly due to carrier-velocity saturation as the resulting base push-out partially offsets base-width modulation. This effect is also demonstrated in simulations with PISCES and MMSPICE     

Continuity of the Solution Map in Parametric Affine Variational Inequalities

A systematic study of the upper semicontinuity and the lower semicontinuity of the solution map in parametric affine variational inequalities is given in this paper. Several examples are constructed to analyze the results. This work was supported by Korea Research Foundation Grant (KRF 2001-015-DP0049), the APEC Postdoctoral Fellowships Program, and the KOSEF Brain Pool Program.