The implementation of TS MAC (transmitter station monitor, alarmand control) system for digital DBS system

The implementation of TS MAC system for KOREASAT DBS (direct broadcast satellite) system is presented. This TS MAC controls and monitors the status of the TS equipment and gathers the alarm for them. The advantage of this system is the center-concentrated, real time processing, remote control, and object oriented module decomposing     

Solid phase synthesis of azapeptides using an automatic synthesizer

Peptides containing azaglycine located terminally or within the backbone have been prepared in the solid phase by means of an automatic synthesizer.     

Spatial retardation of carrier heating in scaled 0.1-μmn-MOSFET's using Monte Carlo simulations

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V_d considerably less than the Si/SiO₂ injection barrier height φ_b. Simulation of both devices reveal that 1) although qV_d<φ_b, carriers can obtain energies greater than φ_b, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates     

Electrical characterization of very-narrow-gap bulk HgCdTe single crystals by variable magnetic field hall measurements

Variable-magnetic-field Hall measurements (0 to 1.5 T) are performed on very-narrow-gap bulk-grown Hg_1−xCd_xTe single crystals (0.165 ≤ x ≤ 0.2) at various temperatures (10 to 300K). The electron densities and mobilities are obtained within the one-carrier (electrons) approximation of the reduced-con-ductivity-tensor scheme. The present data together with the selected data set reported by other workers exhibit a pronounced peak when the electron mobility is plotted against the alloy composition x-value which has been predicted to be due to the effective-mass minimum at the bandgap-crossing (E_g ≈ 0). The observed position (x ≈ 0.165), height (≈4 x 10² m²Vs), and width (≈0.01 in x) of the mobility-peak can be explained by a simple simulation involving only ionized-impurity scattering. A lower bound of the effective mass is introduced as a fitting parameter to be consistent with the finiteness of the observed electron mobility and is found to be of the order of 10⁻⁴ of the mass of a free electron.     

Interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd0.96Zn0.04 Te (211)B substrates by molecular beam epitaxy

Double-crystal x-ray rocking curve (DCRC) and secondary-ion mass-spectroscopy (SIMS) measurements have been performed to investigate the effect of rapid thermal annealing on the interdiffusion behavior of Hg in HgTe/CdTe superlattices grown on Cd_0.96Zn_0.04Te (211)B substrates by molecular beam epitaxy. The sharp satellite peaks of the DCRC measurements on a 100-period HgTe/CdTe (100Å/100Å) superlattice show a periodic arrangement of the superlattice with high-quality interfaces. The negative direction of the entropy change obtained from the diffusion coefficients as a function of the reciprocal of the temperature after RTA indicates that the Hg diffusion for the annealed HgTe/CdTe superlattice is caused by an interstitial mechanism. The Cd and the Hg concentration profiles near the annealed HgTe/CdTe superlattice interfaces, as measured by SIMS, show a nonlinear behavior for Hg, originating from the interstitial diffusion mechanism of the Hg composition. These results indicate that a nonlinear interdiffusion behavior is dominant for HgTe/CdTe superlattices annealed at 190°C and that the rectangular shape of HgTe/CdTe superlattices may change to a parabolic shape because of the intermixing of Hg and Cd due to the thermal treatment.     

AN ALTERNATIVE SPECIFICATION FOR MODELING GROUNDWATER DYNAMICS

This research extends previous work with dynamic models to manage groundwater quality by using the consumptive nitrate use rate instead of the nitrate application rate. The analysis indicates that misspecification results in overestimation of economic benefits, and supra-optimum nitrogen fertilizer application rates and groundwater nitrate stocks at a steady state.     

Multiple recurrence and infinite measure preserving odometers

A family of infinite measure preserving odometers is presented which exhibit examples ofp-recurrent but notp+1-recurrent ergodic transformations for everyp>1.     

A possibility of parallel and anti-parallel diffraction measurements on neutron diffractometer employing bent perfect crystal monochromator at the monochromatic focusing condition

In a conventional diffractometer having single monochromator, only one position, parallel position, is used for the diffraction experiment (i.e. detection) because the resolution property of the other one, anti-parallel position, is very poor. However, a bent perfect crystal (BPC) monochromator at monochromatic focusing condition can provide a quite flat and equal resolution property at both parallel and anti-parallel positions and thus one can have a chance to use both sides for the diffraction experiment. From the data of the FWHM and the Δd/d measured on three diffraction geometries (symmetric, asymmetric compression and asymmetric expansion), we can conclude that the simultaneous diffraction measurement in both parallel and anti-parallel positions can be achieved.     

Design,Implementation, and Validation of KOMPSAT‐2 Software Simulator

In this paper, we present design features, implementation, and validation of a satellite simulator subsystem for the Korea Multi‐Purpose Satellite‐2 (KOMPSAT‐2). The satellite simulator subsystem is implemented on a personal computer to minimize costs and trouble on embedding onboard flight software into the simulator. An object‐oriented design methodology is employed to maximize software reusability. Also, instead of a high‐cost commercial database, XML is used for the manipulation of spacecraft characteristics data, telecommand, telemetry, and simulation data. The KOMPSAT‐2 satellite simulator subsystem is validated by various simulations for autonomous onboard launch and early orbit phase operations, anomaly operation, and science fine mode operation. It is also officially verified by successfully passing various tests such as the satellite simulator subsystem test, mission control element system integration test, interface test, site installation test, and acceptance test.     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.