Effects of isothermal aging and temperature–humidity treatment of substrate on joint reliability of Sn–3.0Ag–0.5Cu/OSP-finished Cu CSP solder joint

This study examined the effects of isothermal aging and temperature–humidity (TH) treatment of substrate on the joint reliability of a Sn–3.0Ag–0.5Cu (wt.%)/organic solderability preservative (OSP)-finished Cu solder joint. Two types of OSP-finished chip-scale-package (CSP) substrates were used, those subjected and not subjected to the TH test. This study revealed an association between the interfacial reaction behaviors, void formation and mechanical reliability of the solder joint. Many voids were formed at the interface of the OSP-finished Cu joint subjected to the TH test. These voids were caused by the oxidation of the OSP-finished Cu substrate during the TH test. In the shear tests, the shear force of the joint with the substrate not subjected to the TH test was slightly higher than that with the TH test. The mechanical reliability of the solder joint was degraded by voids at the interface.     

Mechanical reliability of Sn-rich Au–Sn/Ni flip chip solder joints fabricated by sequential electroplating method

In this study, we evaluated the mechanical reliability of Sn-rich, Au–Sn/Ni flip chip solder bumps by using a sequential electroplating method with Sn and Au. After reflowing, the average diameter of the solder bump was approximately 80 μm and only a (Ni,Au)₃Sn₄ intermetallic compound (IMC) layer was formed at the interface. Due to the preferential consumption of Sn atoms within the solder matrix during aging, the solder matrix was transformed sequentially in the following order: β-Sn and η-phase, η-phase, and η-phase and ε-phase. In the bump shear test, the shear force was not significantly changed despite aging at 150 °C for 1000 h and most of the fractures occurred at the interfaces. The interfacial fracture was significantly related to the formation of brittle IMCs at the interface. The Sn-rich, Au–Sn/Ni flip chip joint was mechanically much weaker than the Au-rich, Au–Sn/Ni flip chip joint. The study results demonstrated that the combination of Sn-rich, Au–Sn solder and Ni under bump metallization (UBM) is not a viable option for the replacement of the conventional, Au-rich, Au–20Sn solder.     

Enhancement of the Performance of a Reflective SOA-Based Hybrid WDM/TDM PON System With a Remotely Pumped Erbium-Doped Fiber Amplifier

A passive optical network (PON) architecture based on a hybrid wavelength-division multiplexing (WDM) and time-division multiplexing (TDM) PON system with a remotely pumped erbium-doped fiber amplifier (EDFA) is presented as an excellent candidate for use in a next-generation optical access network. The remotely pumped EDFA operates as a bidirectional amplifier and provides a 15-dB gain to both upstream signals and seed light sources, so the sensitivity of upstream transmission is greatly improved. An upstream transmission of 1.25 Gb/s with a low seed channel power of -14 dBm is made feasible over a total reach of 25 km for 32-WDM channels and 16-TDM splits by the use of the remotely pumped EDFA. This scheme has advantages that it uses a single transmission fiber for both down-and up-stream signals and that it reduces the Rayleigh scattering contribution.     

Inverted Staggered Poly-Si Thin-Film Transistor With Planarized SOG Gate Insulator

In this letter, we have studied the inverted staggered thin-film transistor (TFT) using a spin-on-glass (SOG) gate insulator and a low-temperature polycrystalline silicon (poly-Si) by Ni-mediated crystallization of amorphous silicon. The p-channel poly-Si TFT exhibited a field-effect mobility of 48.2 cm²/V ldr s, a threshold voltage of -4.2 V, a gate-voltage swing of 1.2 V/dec, and a minimum off-current of < 4 times 10^-13A/ mum at V_ds = -0.1 V. Therefore, the gate planarization technology by SOG can be applicable to low-cost large-area poly-Si active-matrix displays.     

Profit Aware Circuit Design Under Process Variations Considering Speed Binning

In this paper, a profit-aware design metric is proposed to consider the overall merit of a design in terms of power and performance. A statistical design methodology is then developed to improve the economic merit of a design considering frequency binning and product price profile. A low-complexity sensitivity-based gate sizing algorithm is developed to improve economic gain of a design over its initial yield-optimized design. Finally, we present an integrated design methodology for simultaneous sizing and bin boundary determination to enhance profit under an area constraint. Experiments on a set of ISCAS'85 benchmarks show in average 19% improvement in profit for simultaneous sizing and bin boundary determination, considering both leakage power dissipation and delay bounds compared to a design initially optimized for 90% yield at iso-area in 70-nm bulk CMOS technology.     

A fast‐convergent fairness scheme for resource allocation in RPR networks

In this paper, we propose a fast‐convergent fairness scheme in IEEE 802.17 resilient packet ring (RPR) networks. In the proposed scheme, each station could rapidly approach fair rate by estimating the number of unbounded flows at each link. In addition, the fast‐convergent scheme could prevent rate oscillations in the RPR aggressive mode scheme under unbalanced traffic. The estimation mechanism is simple and scalable since it is stateless without per‐flow management. Through analytical and simulation evaluations our scheme was found to be stable and speedy when compared with 802.17 RPR fairness scheme or the proposed distributed virtual‐time scheduling in rings scheme. Our scheme could allocate bandwidth fairly and smoothly among flows and achieve high utilization at the same time in the RPR network. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐Power 512‐Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.     

Analysis of Failure Mechanism in Anisotropic Conductive and Non-Conductive Film Interconnections

Failure behaviors of anisotropic conductive film (ACF) and non-conductive film (NCF) interconnects were investigated by measuring the connection resistance. The four-point probe method was used to measure the connection resistance of the adhesive joints constructed with Au bump on Si chip and Cu pad on flexible printed circuit. The interconnection reliability was evaluated by multiple reflow process. The connection resistance of the ACF joints was markedly higher than that of NCF joints, mainly due to the constriction of the current flow and the intrinsic resistance of the conductive particles in ACF joints. The connection resistances of both interconnections decreased with increasing bonding force, and subsequently converged to about 10 and 1 mOmega at a bonding force of 70 and 80 N, for the ACF and NCF joints, respectively. During the reflow process, two different conduction behaviors were observed: increased connection resistance and the termination of Ohmic behavior. The former was due to the decreased contact area caused by z-directional swelling of the adhesives, whereas the latter was caused by either contact opening in the adhesive joints or interface cracking.     

Chiral Brønsted acid-catalyzed Friedel–Crafts reaction of 3-indolylsulfamidates with indoles: Synthesis of enantioenriched bisindolylmethane sulfamates

A Brønsted acid-catalyzed asymmetric Friedel–Crafts alkylation of 3-indolylsulfamidates with indoles has been established toward the efficient synthesis of biologically important bisindolylarylmethane derivatives containing the phenylsulfamate group. The reaction using chiral BINOL-derived phosphoric acid as the catalyst was tolerant to a diverse range of 3-indolylsulfamates and indoles, and provided for the first time bisindolylarylmethane sulfamate derivatives in good yields and with moderate to high enantioselectivities (up to 89% yield, 94:6 er). Moreover, some of these novel compounds were evaluated for their biological activities and confirmed to show bioactivity for preventing peripheral nerve degeneration.     

Visualizing Microglia with a Fluorescence Turn‐On Ugt1a7c Substrate

Microglia, the brain‐resident macrophage, are involved in brain development and contribute to the progression of neural disorders. Despite the importance of microglia, imaging of live microglia at a cellular resolution has been limited to transgenic mice. Efforts have therefore been dedicated to developing new methods for microglia detection and imaging. Using a thorough structure–activity relationships study, we developed CDr20, a high‐performance fluorogenic chemical probe that enables the visualization of microglia both in vitro and in vivo. Using a genome‐scale CRISPR‐Cas9 knockout screen, the UDP‐glucuronosyltransferase Ugt1a7c was identified as the target of CDr20. The glucuronidation of CDr20 by Ugt1a7c in microglia produces fluorescence.