On error bounds for lower semicontinuous functions

We give some sufficient conditions for proper lower semicontinuous functions on metric spaces to have error bounds (with exponents). For a proper convex function f on a normed space X the existence of a local error bound implies that of a global error bound. If in addition X is a Banach space, then error bounds can be characterized by the subdifferential of f. In a reflexive Banach space X, we further obtain several sufficient and necessary conditions for the existence of error bounds in terms of the lower Dini derivative of f. Received: April 27, 2001 / Accepted: November 6, 2001?Published online April 12, 2002     

通过直接栅电流测量研究PMOSFET's热载流子损伤

通过直接栅电流测量方法研究了热载流子退化和高栅压退火过程中PMOSFET's热载流子损伤的生长规律.由此,给出了热载流子引起PMOSFET's器件参数退化的准确物理解释.并证明了直接栅电流测量是一种很好的研究器件损伤生长和器件参数退化的实验方法.     

npn AlGaN/GaN HBT模型与特性分析

基于实验数据对GaN材料的少子寿命和碰撞电离率进行了建模,应用漂移-扩散传输模型开展了npnAlGaN/GaN异质结双极晶体管的特性研究,给出了器件导通电压、偏移电压和饱和电压的解析式.结果表明:实际器件导通电压、偏移电压及饱和电压较大的原因主要是高基区电阻和基区接触的非欧姆特性,为器件的工艺制造提供了理论指导.     

HfOxNy的场发射特性

用直流溅射和高温退火相结合的方法制备了HfOxNy薄膜并测试了其场发射性能,发现其具有较低的开启电场、较大的发射电流密度以及很好的发射稳定性.高压"锻炼"对提高HfOxNy场发射性能起着关键作用,这与高压"锻炼"下薄膜内部结构和表面性质的改变有关.对场发射机理的研究表明,HfOxNy的场发射符合经典的FN隧穿理论.     

Efficient 3-d capacitance extraction considering lossy substrate with multilayered green's function

An efficient algorithm for extraction of three-dimensional (3-D) capacitance on multilayered and lossy substrates is presented. The new algorithm presents a major improvement over the quasi-3-D approach used in a Green's function-based solver and takes into consideration the sidewalls of 3-D conductors. To improve the efficiency of the computation and the transformation of the Green's function, a nonuniform grid is adopted. The most computationally intensive part in the transformation of the Green's function is computed separately as technology-independent matrices Tk foremost. Once computed, Tk can be stored and used for any technology, thus the storage requirement and computational complexity are reduced from O (S/sup 2/) and O (S/sup 2/ log S/sup 2/), respectively, to just O [(log S/sub max/)/sup 2/]. Extensive tests have been performed to verify the new algorithm, and its accuracy has been established by comparing with other programs.     

Development of a low cost microwave mixer using a broad-band substrate integrated waveguide (SIW) coupler

A low cost single-balanced mixer is designed using a newly designed 90/spl deg/ substrate integrated waveguide (SIW) 3-dB coupler, which takes the advantages of low cost, low profile, and high performance. An X-band single-balanced SIW mixer is designed and fabricated with a standard printed circuit board process. Measured conversion loss of 6.8dB and the wide-band response from 8.5 to 12GHz are presented.     

Performance of Alamouti transmit diversity over time-varying Rayleigh-fading channels

We analyze the impact of a time-varying Rayleigh-fading channel on the performance of an Alamouti transmit-diversity scheme. We propose several optimal and suboptimal detection strategies for mitigating the effects of a time-varying channel, and derive expressions for their bit-error probability as a function of the channel correlation coefficient /spl rho/. We find that the maximum-likelihood detector that optimally compensates for the time-varying channel is very tolerant to time-varying fading, attaining full diversity order even for the extreme case of /spl rho/=0. In contrast, although lower in complexity, the suboptimal schemes suffer a diversity penalty and are thus suitable only for slowly fading channels.     

MCM用氮化铝共烧多层陶瓷基板的研究

通过实验优化AlN(氮化铝)瓷料配方及排胶工艺,对共烧W(钨)导体浆料性能及AlN多层基板的高温共烧工艺进行了研究,并对AlN多层基板的界面进行了扫描电镜分析。采用AlN流延生瓷片与W高温共烧的方法,成功地制备出了高热导率的AlN多层陶瓷基板,其热导率为190 W/(m·K),线膨胀系数为4.6106℃1(RT~400℃),布线层数9层,W导体方阻为9.8 m,翘曲度为0.01 mm/50 mm,完全满足高功率MCM的使用要求。     

一个面积和功耗优化且适用于10/100 Base-T以太网的CMOS时钟恢复电路

提出了一个新的用于10 / 10 0 Base- T以太网中面积和功耗优化的时钟恢复电路.它采用双环路的结构,加快了锁相环路的捕获和跟踪速度;采用复用的方式,通过选择信号控制电路可分别在10 Mbps或10 0 Mbps模式下独立工作且能方便地实现模式间的互换,与采用两个独立的CDR电路相比节省了一半的面积;同时,电路中采用一般的延迟单元来取代DL L,并能保证环路性能不随工艺温度等条件引起的延迟单元、延迟时间的变化而变化,从而节省了功耗.Hspice模拟结果显示,在Vdd=2 .5 V时,10 0 Mbps模式下电路的功耗约为75 m W,稳态相差为0 .3 ns;10 Mbps模式时电路功耗为5 8m W     

Design, modeling, and hardware correlation of a 3.2Gb/s/pair memory channel

With the rapid advance of silicon process technology, it is now possible to design input/output (I/O) circuits that operate at multigigabit data rates. As a result, accurate modeling and analysis of high-speed interconnect systems is essential to optimize the performance of the overall system. This paper describes the interconnect design, modeling, simulation, and characterization methodologies that are essential to achieve multigigabit data rates. It focuses on the physical layer verification and hardware correlation of functional systems and silicon to ensure robust system operation over 3.2Gb/s data rate using conventional low-cost packaging and printed circuit board (PCB) technologies. In order to capture conductor and dielectric losses, as well as other high-frequency effects of three-dimensional structures, accurate measurement-based simulation techniques that directly incorporate frequency-domain parameters from measurement or electromagnetic solver parameters into circuit simulation tools using fast Fourier transform (FFT) and bandlimiting windowing techniques are developed. Finally, simulation waveforms are correlated with prototypes at both component and system levels in both time and frequency domains.